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24-Bit, Single-Channel, Ultra-Low-Power, Delta

Sigma ADC with 2-Wire Serial Interface

Figure 1. Timing Diagram for Data Read After Conversion

Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK

Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration

1

D23

CONVERSION IS DONE

DATA IS AVAILABLE

CONVERSION IS DONE

DATA IS AVAILABLE

D22

D0

2

3

24

SCLK

RDY/DOUT

1

D23

CONVERSION IS DONE

DATA IS AVAILABLE

CONVERSION IS DONE

DATA IS AVAILABLE

D22

D0

2

3

24

25

SCLK

RDY/DOUT

25TH SLK RISING EDGE

PULLS RDY/DOUT

HIGH

1

D23

CONVERSION IS DONE

DATA IS AVAILABLE

CONVERSION IS DONE

DATA IS AVAILABLE AFTER CALIBRATION

CALIBRATION STARTS ON 26TH SCLK

D22

D0

2

3

24

1

2

25

26

D23

D22

SCLK

RDY/DOUT

25TH SCLK PULLS

RDY/DOUT HIGH