HT16512 datasheet(4/11 Pages) HOLTEK

4 / 11 page

A.C. Characteristics

Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VDD

Conditions

tPHL

Propagation Delay Time

CLK

®DO

CL=15pF, RL=10k

¾¾

100

tPLH

¾¾

300

tr1

Rise Time

CL=300pF, S0~S10

¾¾

tr2

CL=300pF, G0~G5,

S11/G10~S15/G6

¾¾

0.5

Fall Time

CL=300pF, Sn, Gn

¾¾

120

tmax

Maximum Clock Frequency

Duty=50%

¾¾

MHz

Input Capacitance

¾¾

tCW

Clock Pulse Width

400

¾¾

tSW

Strobe Pulse Width

¾¾

tSU

Data Setup Time

100

¾¾

Data Hold Time

100

¾¾

tCS

Clock-Strobe Time

CLK rising edge to CS rising edge

¾¾

Wait Time

CLK rising edge to CLK falling edge

¾¾

HT16512

Rev. 1.50

May 7, 2010

Functional Description

Display RAM and Display Mode

The static display RAM is organized into 22

´8 bits and

stores the data transmitted from an external device to

the HT16512 through a serial interface. The contents of

the RAM are directly mapped to the contents of the VFD

driver. Data in the RAM can be accessed through the

data setting, address setting and display control com-

mands. It is assigned addresses in 8-bit unit as follows:

Dimming Control

HT16512 provides 8-step dimmer function on display by

controlling the 3-bit binary command code. The full

pulse width of grid signal is divides into 16 uniform sec-

tions by PWM (pulse width modulation) technology.

The 16 uniform sections available form 8 steps dimmer

via 3-bit binary code. The 8-step dimmer includes 1/16,

2/16, 4/16, 10/16, 11/16, 12/16, 13/16 and 14/16. The

1/16 pulse width indicates minimum lightness. The

14/16 pulse width represents maximum lightness. (Re-

fer to the display control command).

Key Matrix and Key-Input Data Storage RAM

The key matrix scans the series key states at each level

of the key strobe signal (S0/K0~S5/K5) output of the

HT16512. The key strobe signal outputs are

time-multiplexed signals from S0/K0~S5/K5. The states

of inputs K0~K3 are sampled by strobe signal

S0/K0~S5/K5 and latched into the register.

The key matrix is made up of a 6

´4 matrix, as shown be-

low.

S 0

A d d r e s s : 0 0 H

0 2 H

0 4 H

0 6 H

0 8 H

0 A H

0 C H

0 E H

1 0 H

1 2 H

1 4 H

b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7

0 1 H

0 3 H

0 5 H

0 7 H

0 9 H

0 B H

0 D H

0 F H

1 1 H

1 3 H

1 5 H

b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7

D i g i t 0

D i g i t 1

D i g i t 2

D i g i t 3

D i g i t 4

D i g i t 5

D i g i t 6

D i g i t 7

D i g i t 8

D i g i t 9

D i g i t 1 0

S 3 S 4

S 7

S 8

S 1 1 S 1 2

S 1 5

S 5 / K 5

S 4 / K 4

K 3

K 2

K 1

K 0

S 3 / K 3

S 0 / K 0

S 1 / K 1

S 2 / K 2

K e y m a t r i x

D e t a i l

HT16512 Datasheet(PDF) 4 Page - Holtek Semiconductor Inc

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