PIC16F707 datasheet(49/284 Pages) MICROCHIP

49 / 284 page

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 49

PIC16F707/PIC16LF707

5.0

LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The PIC16F707 has an internal Low Dropout Regulator

(LDO) which provides operation above 3.6V. The LDO

regulates a voltage for the internal device logic while

permitting the VDD and I/O pins to operate at a higher

voltage. There is no user enable/disable control

available for the LDO, it is always active. The

PIC16LF707 operates at a maximum VDD of 3.6V and

does not incorporate an LDO.

A device I/O pin may be configured as the LDO voltage

output, identified as the VCAP pin. Although not

required, an external low-ESR capacitor may be

connected to the VCAP pin for additional regulator

stability.

The VCAPEN<1:0> bits of Configuration Word 2

determines which pin is assigned as the VCAP pin.

Refer to Table 5-1.

On power-up, the external capacitor will load the LDO

voltage regulator. To prevent erroneous operation, the

device is held in Reset while a constant current source

charges the external capacitor. After the cap is fully

charged, the device is released from Reset. For more

information on recommended capacitor values and the

constant current rate, refer to the LDO Regulator

Characteristics Table in Section 25.0 “Electrical

Specifications”.

TABLE 5-2:

SUMMARY OF CONFIGURATION WORD WITH LDO

TABLE 5-1:

VCAPEN<1:0> SELECT BITS

VCAPEN<1:0>

RA0

RA5

RA6

No VCAP

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

on Page

CONFIG2

13:8

—

7:0

—

VCAPEN1(1) VCAPEN0(1)

—

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.

Note 1:

PIC16F707 only.

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