IR3529

Page 13 of 22

February 12, 2010

A synchronous rectification disable comparator is used to detect the converter’s CSIN- pin voltage, which

represents local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected,

GATEL is driven low, which disables synchronous rectification and eliminates negative current during power-up.

The gate drivers are pulled low if the supply voltage falls below the normal operating range. An 80k

resistor is

connected across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to

leakage or other causes under these conditions.

PWM Ramp

Every time the phase IC is powered up, the PWM ramp magnitude is calibrated to generate a 52.5 mV/% ramp

(VCC=12V). For example, a 15 % duty ratio will generate a ramp amplitude of 787.5 mV (15 x 52.5 mV) with

12V supply applied to VCC. Feed-forward control is achieved by varying the PWM ramp proportionally with VCC

voltage after calibration.

In response to a load step-up, the error amplifier can demand 100 % duty cycle. As shown in Figure 6, 100 %

duty is detected by comparing the PWM latch output (PWMQ) and its input clock (PWM_CLK). If the PWMQ is

high when the PWM_CLK is asserted, the top FET turnoff is initiated. The top FET is again turned on once the

RMPOUT drops within 200 mV of the VDAC.

PHIN

CLKIN

EAIN

(2 Phase Design)

RMPOUT

PWMQ

100 % DUTY OPERATION

NORMAL OPERATION

Figure 6: PWM Operation during normal and 100 % duty mode.

Power State Indicator (PSI) function

From a system perspective, the PSI input is controlled by the system and is forced low when the load current is

lower than a preset limit and forced high when load current is higher than the preset limit. IR3529 can accept an

active low signal on its PSI input and force the drivers into tri-state, effectively, forcing the phase IC into an off

state. Once the PSI# signal is asserted, the IC waits for 8 PHSIN cycles before forcing the drivers into tri-state.

This delay is required to ensure that the IC does not respond to any high frequency PSI# signal because

entering into PSI mode for a very short duration does not benefit the system efficiency. Irrespective of the PSI#

input, the disabled phase remains connected to the ILL bus which ensures accurate voltage positioning.

However, on assertion of PSI# signal, the disabled phase is disconnected from the ISHARE bus and therefore

ISHARE will represent the actual per phase current information.