IR3529

Page 7 of 22

February 12, 2010

PIN DESCRIPTION

PIN#

PIN SYMBOL

PIN DESCRIPTION

1

ILL

Output of the Current Sense Amplifier is connected to this pin through a 3k

resistor. Voltage on this pin is equal to V(DACIN) + 33 [V(CSIN+) – V(CSIN-)].

Connecting all ILL pins together creates a bus which provides an indication of the

average current being supplied by the power supply. The signal is used by the

Control IC for voltage positioning and over-current protection. OVP mode is initiated

if the voltage on this pin rises above V(VCCL)- 0.8V.

2

PSI#

Digital Power State Indicator input, active low.

3

DACIN

Reference voltage input from the Control IC. The Current Sense signal and PWM

ramp is referenced to the voltage on this pin.

4

LGND

Ground for internal IC circuits. IC substrate is connected to this pin.

5

PHSIN

Phase clock input at switching frequency.

6

SHIFT

Communication input from phase IC(s) statically floats at VCCL/2. Momentarily

pulling pin up to VCCL indicates a phase has entered the daisy chain loop resulting

in an up-shift in the CLKOUT frequency. Momentarily pulling down to ground

indicates a loss of a phase and down-shifts the CLKOUT frequency.

7

PHSOUT

Phase clock output at switching frequency.

8

CLKIN

Clock input.

9

PGND

Return for low side driver and reference for GATEH non-overlap comparator.

10

GATEL

Low-side driver output and input to GATEH non-overlap comparator.

11

OCSET

Programs cycle by cycle Over Current threshold voltage. V(OCSET) gets compared

against the V(SW) node when the high side MOSFET is on. If V(SW) gets below

V(OCSET), the next switch pulse gets skipped to allow inductor relaxation. The

V(OCSET) threshold is programmed by forcing a 200uA current sink through an

external resistor kelvined to the drain of the high side FET.

12

VCCL

Supply for low-side driver. Internal bootstrap synchronous PFET is connected from

this pin to the BOOST pin.

13

BOOST

Supply for high-side driver. Internal bootstrap synchronous PFET is connected

between this pin and the VCCL pin.

14

GATEH

High-side driver output and input to GATEL non-overlap comparator.

15

SW

Return for high-side driver and reference for GATEL non-overlap comparator.

16

VCC

Supply for internal IC circuits.

17

CSIN+

Non-Inverting input to the current sense amplifier, and input to debug comparator.

18

CSIN-

Inverting input to the current sense amplifier, and input to synchronous rectification

disable comparator.

19

EAIN

PWM comparator input from the error amplifier output of Control IC. Body Braking

mode is initiated if the voltage on this pin is less than V(DACIN).

20

ISHARE

Output of the Current Sense Amplifier is connected to this pin through a 3k

resistor. Voltage on this pin is equal to V(DACIN) + 33 [V(CSIN+) – V(CSIN-)].

Connecting all ISHARE pins together creates a share bus which provides an

indication of the average current being supplied by active phases only. The pin

becomes high impedance during PSI# activation.