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CAT9552WI Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT9552WI Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 18 page  CAT9552 Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 4). The CAT9552 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. When the CAT9552 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9552 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT9552 to the standby power mode and place the device in a known state. Registers and Bus Transactions After the successful acknowledgement of the slave address, the bus master will send a command byte to the CAT9552 which will be stored in the Control Register. The format of the Control Register is shown in Figure 5. The Control Register acts as a pointer to determine which register will be written or read. The four least significant bits, B0, B1, B2, B3, are used to select which internal register is accessed, according to the Table 1. If the auto increment flag is set (AI = 1), the four least significant bits of the Control Register are automatically incremented after a read or write operation. This allows the user to access the CAT9552 internal registers sequentially. The content of these bits will rollover to “0000” after the last register is accessed. Table 1. Internal Registers Selection B3 B2 B1 B0 Register Name Type Register Function 0 0 0 0 INPUT0 READ Input Register 0 0 0 0 1 INPUT1 READ Input Register 1 0 0 1 0 PSC0 READ/ WRITE Frequency Prescaler 0 0 0 1 1 PWM0 READ/ WRITE PWM Register 0 0 1 0 0 PSC1 READ/ WRITE Frequency Prescaler 1 0 1 0 1 PWM1 READ/ WRITE PWM Register 1 0 1 1 0 LS0 READ/ WRITE LED 0-3 Selector 0 1 1 1 LS1 READ/ WRITE LED 4-7 Selector 1 0 0 0 LS2 READ/ WRITE LED 8-11 Selector 1 0 0 1 LS3 READ/ WRITE LED 12-15 Selector ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER Figure 4. Acknowledge Timing 00 0 AI B3 B2 B1 B0 AUTO-INCREMENT FLAG RESET STATE: 00h REGISTER ADDRESS Figure 5. Control Register Doc. No. MD-9005 Rev D 8 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice |
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