ATSAM3U datasheet(25/62 Pages) ATMEL

25 / 62 page

6430CS–ATARM–09-Apr-10

SAM3U Series

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It

integrates a permanent pull-down resistor of about 15 k

Ω to GNDBU, so that it can be left uncon-

nected for normal operations.

By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial

Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and

TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire

Debug Port is active, TDO/TRACESWO can be used for trace.

The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous

trace can only be used with SW-DP, not JTAG-DP.

All the JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.

6.4

Test Pin

The TST pin is used for JTAG Boundary Scan Manufacturing Test or fast flash programming

mode of the SAM3U series. The TST pin integrates a permanent pull-down resistor of about 15

Ω to GND, so that it can be left unconnected for normal operations. To enter fast programming

mode, see the “Fast Flash Programming Interface” section of the product datasheet. For more

on the manufacturing and test mode, refer to the “Debug and Test” section of the product

datasheet.

6.5

NRST Pin

The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low

to provide a reset signal to the external components or asserted low externally to reset the

microcontroller. It will reset the Core and the peripherals, except the Backup region (RTC, RTT

and Supply Controller). There is no constraint on the length of the reset pulse and the reset con-

troller can guarantee a minimum pulse length.

The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 k

Ω.

6.6

NRSTB Pin

The NRSTB pin is input only and enables asynchronous reset of the SAM3U when asserted low.

The NRSTB pin integrates a permanent pull-up resistor of about 15 k

Ω. This allows connection

of a simple push button on the NRSTB pin as a system-user reset. In all modes, this pin will

reset the chip including the Backup region (RTC, RTT and Supply Controller). It reacts as the

Power-on reset. It can be used as an external system reset source. In harsh environments, it is

recommended to add an external capacitor (10 nF) between NRSTB and VDDBU. (For filtering

values refer to “I/O Characteristics” in the “Electrical Characteristics” section of the product

datasheet.)

It embeds an anti-glitch filter.

6.7

ERASE Pin

The ERASE pin is used to reinitialize the Flash content and some of its NVM bits. It integrates a

permanent pull-down resistor of about 15 k

Ω to GND, so that it can be left unconnected for nor-

mal operations.

This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high

during less than 100 ms, it is not taken into account. The pin must be tied high during more than

220 ms to perform the reinitialization of the Flash.

ATSAM3U Datasheet(PDF) 25 Page - ATMEL Corporation

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