BQ76PL536PAP datasheet(16/58 Pages) TI

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470 nF

RTH

REG50

TS+

TS–

RB =.4 (RTH @ 40C – RTH@ 90C)

RT = RTH@ 40C – 2RTH @90C – RB

bq76PL536

SLUSA08A – DECEMBER 2009 – REVISED JULY 2010

www.ti.com

Figure 5. Thermistor Connection

Converting TSn Result to Voltage (Ratio)

To convert the returned TSn measurement value to a ratio, RTS = VTS:REG50, the following formula is used.

ADC behavior: COUNT = VTS / REG50 × 33,104

RTS = (REGMSB × 256 + REGLSB) / 16,548

FUNCTION_CONFIG[] = 0100 xxxxb

Example:

The voltage connected to the TSn inputs (TSn+ – TSn–) == 0.6609 V; VREG50 ≈ 5 V nominal

After conversion, REGMSB == 0x11; REGLSB == 0x18

ACTUAL_COUNT = 0x11 × 0x100 + 0x18 = 0x1118 (4376)

4376 / 33,104 = 0.1322 (ratio of TSn inputs to REG50)

0.1322 × REG50 = 0.6609 V

ADC Band-Gap Voltage Reference

The ADC and protection subsystems use separate and independent internal voltage references. The ADC

bandgap (VREF) is nominally 2.5 V. The reference is temperature-compensated and stable.

The internal reference is brought out to the VREF pin for bypassing. A high quality 10-mF capacitor should be

connected between the VREF and AGND pins, in close physical proximity to the device pins, using short track

lengths to minimize the effects of track inductance on signal quality. AGND should be connected to VSS. Device

VSS connections should be brought to a single point close to the IC to minimize layout-induced errors. The

device tab should also be connected to this point, and is a convenient common VSS location. The internal VREF

should not be used externally to the device by user circuits.

Conversion Control

Convert Start

Two methods are available to start a conversion cycle. The CONV_H pin may be asserted, or firmware may set

the CONVERT_CTRL[CONV] bit.

Hardware Start

A single interface pin (CONV_H) is used for conversion-start control by the host. A conversion cycle is started by

a hardware signal when the CONV_H is transitioned low-to-high by the host. The host should hold this state until

the conversion cycle is complete to avoid erroneous edges causing a conversion start when the present

conversion is not complete. The signal is simultaneously sent to the higher device in the stack by the assertion of

the CONV_N signal. The bq76PL536 automatically sequences through the series of measurements enabled via

the ADC_CONTROL[] register after a convert-start signal is received from either the register bit or the hardware

pin.

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