BQ76PL536PAP datasheet(27/58 Pages) TI

27 / 58 page

bq76PL536

www.ti.com

SLUSA08A – DECEMBER 2009 – REVISED JULY 2010

Application Notes on the Host SPI Interface Pin States

The CS_H pin is active-low. The host asserts the pin to a logic zero to initiate communications. The CS pin

should remain low until the end of the current packet. When the CS_H pin is asserted, the SPI receiver and

interface of the device are reset and resynchronized. This action ensures that a slave device that has lost

synchronization during a previous transmission or as the result of noise on the bus does not remain permanently

hung. CS_H must be driven false (high) between packets; see AC Timing Characteristics for timing details.

Device-to-Device Vertical Bus (VBUS) Interface

Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides

common-mode voltage isolation between successive bq76PL536s. This vertical bus (VBUS) is found on the _N

and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and

DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed.

The _S (South-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of

bq76PL536s. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped; _S

always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the

same name, but opposite suffix. All pins operate within the voltages present at the BAT and VSS pins. Use

caution; these pins may be several hundred volts above system ground, depending on their position in

the stack.

Designer Note: North (_N) pins of the top, most-positive device in the stack should be connected to the

BAT1(2) pins of the device for correct operation of the string. South (_S) pins of the lowest, most-negative

device in the stack should be connected to VSS of the device. The connections may direct, or via a pullup

resistor (_N) or pulldown resistor (_S) in the range of 100 Ω–1 MΩ.

The maximum SCLK frequency is limited by the number of devices in the vertical stack and other factors. Each

device imposes an approximately 30-nS delay on the round trip communications speed, i.e., from SCLK rising

(an input to all devices) to the SDO pin transitioning requires ~30 ns per device. The designer must add to this

the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in series with

the connection, and any other wiring or cabling between devices in the system. To maximize speed, these other

system components should be carefully selected to minimize delays and other detrimental effects on signal

quality. Wiring and connectors should receive special attention to their transmission line characteristics.

Other factors which should be considered are clock duty cycle, clock jitter, temperature effects on clock and

system components, user-selected drive level for the level-shift interface, and desired design margin.

The VBUS SPI interface is placed in a low-power mode when CS_H is not asserted on the base device.

The CS_N/S pins are asserted by a logic high on the vertical interface bus (logically inverted from CS_H). This

creates a default VBUS CS condition of logic low, reducing current consumption to a minimum.

To reduce power consumption of the SPI interface to a minimum, the SCLK_H and SDI_H should be maintained

at a logic low (de-asserted). The VBUS versions of these signals are not inverted from the host interface. The

device also de-asserts by default the SDO_N/S pins to minimize power consumption.

Packet Formats

Data Read Packet

When the bq76PL536 is selected (CS_S [CS_H for first device] is active and the bq76PL536 has been

addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N

pin of the next device down the stack. This continues to the first device in the stack, where the data in from the

SDO_N pin is transmitted to the host via the SDO_H pin. The device supplying the read data generates a CRC

as the last byte sent.

Submit Documentation Feedback

Product Folder Link(s) :bq76PL536

BQ76PL536PAP Datasheet(PDF) 27 Page - Texas Instruments

BQ76PL536PAP Datasheet(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL