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DAC7568 Datasheet(PDF) 7 Page - Texas Instruments

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Part # DAC7568
Description  12-/14-/16-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTERS with 2.5V, 2ppm/째C Internal Reference
PDF  58 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC7568 Datasheet(HTML) 7 Page - Texas Instruments

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TIMING DIAGRAM
SCLK
SYNC
DIN
DB31
DB0
LDAC
(1)
LDAC
(2)
CLR
t
2
t
7
t
6
t
9
t
10
t
8
t
4
t
5
t
3
t
1
t
12
t
14
t
15
t
13
t
11
TIMING REQUIREMENTS
(1) (2)
DAC7568
DAC8168
DAC8568
www.ti.com ..................................................................................................................................................... SBAS430A – JANUARY 2009 – REVISED APRIL 2009
(1)
Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
(2)
Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
Figure 1. Serial Write Operation
At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
DAC7568/DAC8168/DAC8568
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCLK falling edge to SYNC falling edge (for
t1
AVDD = 2.7V to 5.5V
10
ns
successful write operation)
t2
(3)
SCLK cycle time
AVDD = 2.7V to 5.5V
20
ns
SYNC rising edge to 31st SCLK falling edge
AVDD = 2.7V to 5.5V
13
t3
ns
(for successful SYNC interrupt)
t4
Minimum SYNC HIGH time
AVDD = 2.7V to 5.5V
80
ns
t5
SYNC to SCLK falling edge setup time
AVDD = 2.7V to 5.5V
13
ns
t6
SCLK LOW time
AVDD = 2.7V to 5.5V
8
ns
t7
SCLK HIGH time
AVDD = 2.7V to 5.5V
8
ns
t8
SCLK falling edge to SYNC rising edge
AVDD = 2.7V to 5.5V
10
ns
t9
Data setup time
AVDD = 2.7V to 5.5V
6
ns
t10
Data hold time
AVDD = 2.7V to 5.5V
4
ns
SCLK falling edge to LDAC falling edge for
t11
AVDD = 2.7V to 5.5V
40
ns
asynchronous LDAC update mode
t12
LDAC pulse width LOW time
AVDD = 2.7V to 5.5V
80
ns
LDAC falling edge to SCLK falling edge for
t13
AVDD = 2.7V to 5.5V
4 × t1
ns
synchronous LDAC update mode
t14
32nd SCLK falling edge to LDAC rising edge
AVDD = 2.7V to 5.5V
40
ns
t15
CLR pulse width LOW time
AVDD = 2.7V to 5.5V
80
ns
(1)
All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2)
See the Serial Write Operation timing diagram.
(3)
Maximum SCLK frequency is 50MHz at AVDD = 2.7V to 5.5V.
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s): DAC7568 DAC8168 DAC8568



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