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LMH6629SD Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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LMH6629SD Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 22 page ![]() Symbol Parameter Conditions Min (Note 6) Typ (Note 6) Max (Note 6) Units NF Noise Figure R S = RT = 50Ω 8.0 dB ANALOG I/O CMVR Input voltage range CMRR > 70 dB −0.30 3.8 V V O Output voltage range R L = 100Ω to VS/2 0.89 0.95 0.82 to 4.19 4.0 3.9 V No Load 0.76 0.85 0.72 to 4.28 4.1 4.0 I OUT Linear output current V O = 2.5V (Note 3) 250 mA V OS Input offset voltage ±150 ±780 ±800 µV TcV OS Input offset voltage temperature drift (Note 7) ±0.45 μV/°C I BI Input bias current (Note 6) −15 −23 −37 μA I OS Input offset current ±0.1 ±1.8 ±3.0 μA T CIOS Input offset voltage temperature drift (Note 7) ±2.8 nA/°C C CM Input capacitance Common Mode 1.7 pF R CM Input resistance Common Mode 450 k Ω MISCELLANEOUS PARAMETERS CMRR Common mode rejection ratio V CM from 0V to 3.7V 82 70 87 dB PSRR Power supply rejection ratio 81 78 83 A VOL Open loop gain 74 72 78 DIGITAL INPUTS/TIMING V IL Logic low-voltage threshold PD and COMP pins 0.8 V V IH Logic high-voltage threshold PD and COMP pins 2.5 I IL Logic low-bias current PD and COMP pins = 0.8V (Note 6) −23 −19 −28 −34 −38 µA I IH Logic high-bias current PD and COMP pins = 2.5V (Note 6) −16 −14 −22 −27 −29 T en Enable time 75 ns T dis Disable time 80 POWER REQUIREMENTS I S Supply Current No Load, Normal Operation (PD Pin = HI or open) 15.5 16.7 18.2 mA No Load, Shutdown (PD Pin =LO) 1.1 1.85 2.0 www.national.com 4 |
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