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KT8554 Datasheet(PDF) 4 Page - Samsung semiconductor |
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KT8554 Datasheet(HTML) 4 Page - Samsung semiconductor |
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4 / 10 page  KT8554B/7B 1 CHIP CODECS TIMING CHARACTERISTICS (Unless otherwise noted, V CC = 5.0 ±5%, VBB = -5.0V ±5%, GNDA = 0V, Ta = 0 oC to 70 oC; typical characteristics specified at V CC = 5.0V, VBB = -5.0V, Ta = 25 oC; all signals referenced to GNDA.) Characteristic Symbol Test Conditions Min Typ Max Unit Frequency of Master Clocks f MCK Depends on the device used and the BCLK R /CLKSEL Pin. MCLK X and MCLKR 1.536 1.544 2.048 MHz MHz MHz Rise Time of Bit Clock t R (BCK) t PB = 488ns 50 ns Fall Time of Bit Clock t F (BCK) t PB = 488ns 50 ns Holding Time from Bit Clock Low to Frame Sync 0 ns Holding Time from Bit Clock High to Frame Sync 0 ns Set-Up Time from Frame Sync to Bit Clock Low 80 ns Delay Time from BCLK X High to Data Valid 0 180 ns Delay Time to TS X Low t D (TSXL) Load = 150pF plus 2 LSTTL loads 140 ns Delay Time from BCLK X Low to Data Output Disabled 50 165 ns Delay Time to Valid Data from FS X or BCLKX, Whichever Comes Later t D (VD) C L = 0pF to 150pF 20 165 ns Set-Up Time from D R Valid to BCLK R/X Low 50 ns Hold Time from BCLK R/X Low to D R Invalid 50 ns Set-Up Time from FS X/R to BCLK X/R Low Short frame sync pulse (1 or 2 bit clock periods long) (Note1) 50 ns Width of Master Clock High t W (MCKH) MCLK X and MCLKR 160 ns Width of Master Clock Low t W (MCKL) MCLK X and MCLKR 160 ns Rise Time of Master Clock t R (MCK) MCLK X and MCLKR 50 ns Fall Time of Master Clock t F( MCK) MCLK X and MCLKR 50 ns Set-Up Time from BCLK X High (and FS X In Long Frame Sync Mode) to MCLK X Falling Edge t SU (BHMF) Period of Bit Clock t CK 485 488 15,72 5 ns Width of Bit Clock High t W (BCKH) V IH = 2.2V 160 ns Width of Bit Clock Low t W (BCKL) V IL = 0.6V 160 ns t H (LFS) t H (HFS) t SU (FBCL) t D (HDV) t D (LDD) t SU (DR BL) t H (BL DR) t SU (FBLS) Long frame only Short frame only Long frame only Load = 150pF plus 2 LSTTL loads First bit clock after the leading edge of FS X |
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