PT6909

V1.1

4

April 2010

FUNCTION DESCRIPTION

POWER TOPOLOGY

PT6909 is optimized to drive non-isolated topology, cascading an input PFC boost stage and an output buck converter

power stage. This power converter topology offers numerous advantages useful for driving high-brightness LED. These

advantages include power factor correction, low harmonic distortion of the input AC line current. The power converter

topology also permits reducing the size of a filter capacitor needed, enabling use of non-electrolytic capacitors. The latter

advantage greatly improves reliability of the overall solution.

PT6909 is a peak current-mode controller that is specifically designed to drive a constant current buck power converter.

PT6909 controls two identical current sense comparators for detecting input and output current. One of the comparators

regulates the output LED current, while the other is used for sensing the input inductor current. The comparator sensing

the input inductor current is mainly responsible for the converter start-up. The control scheme can achieve a low inrush

current, also avoid a high input current while the AC input is under-voltage.

OVER VOLTAGE DETECTION

PT6909 includes output over voltage detection function. The OVP pin is used for sensing the output voltage of boost

stage. The PT6909 will latch the GD output at shutdown state when the output voltage reaches OVP threshold voltage.

In the typical application circuit, the system will go into hiccup mode if the LED load is open. When the LED load is

disconnected, the output voltage rises as the output capacitor C1 starts charging. When the PT6909 detects an over

voltage condition and turns off the converter. The PT6909’s power supply VIN drops under UVLO threshold voltage and

goes into low current start-up status. The PT6909 restarts and turns on the converter. The system starts another cycle

until the LED load is re-connected.

INPUT VOLTAGE LIMITATION

PT6909 built-in power-supply clamped circuit. In the typical application circuit, when the VIN voltage rises higher than

14V typically, it will be clamped at this level with internal 5mA current sink capability.

SETTING INPUT AND OUTPUT CURRENT

Two current sense comparators are included in the PT6909. Both comparators have their inverting inputs internally

connected to 240mV. The CS1 and CS2 inputs are non-inverting inputs of the comparators. When either the CS1 or CS2

pin voltage rises up 240mV, the GD pulse is terminated. A leading edge blanking delay of 300ns(typ) is added. The GD

voltage becomes high again upon receiving the next clock pulse of the oscillator circuit.

Referring to the Typical Application Diagram, the CS1 comparator is responsible for regulating output current. The

output LED current can be programmed using the following equation:

1

CS1

LED

2

1

R

0.24

L

I

I

Δ

−

=

Therefore, the PT6909 starts-up in the input current limiting mode. The CS2 voltage sensing must be programmed such

programmed using the following equation:

L2P

CS2

I

0.24

<

R