SST25WF080 datasheet(15/29 Pages) SST

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Advance Information

8Mbit 1.8V SPI Serial Flash

SST25WF080

S71203-03-000

04/10

64-KByte Block-Erase

The Block-Erase instruction clears all bits in the selected 64

KByte block to FFH. A Block-Erase instruction applied to a

protected memory area is ignored. Prior to any Write oper-

ation, the Write-Enable (WREN) instruction must be exe-

cuted. CE# must remain active low for the duration of any

command sequence. The Block-Erase instruction is initi-

ated by executing an 8-bit command, D8H, followed by

address bits [A23-A0]. Address bits [AMS-A16] (AMS =Most

Significant Address) are used to determine block address

(BAX), remaining address bits can be VIL or VIH. CE# must

be driven high before the instruction is executed. Poll the

Busy bit in the software status register or wait TBE for the

completion of the internal self-timed Block-Erase. See Fig-

ure 16 for the Block-Erase sequences.

FIGURE 16: 64-KByte Block-Erase Sequence

Chip-Erase

The Chip-Erase instruction clears all bits in the device to

FFH. A Chip-Erase instruction is ignored if any of the mem-

ory area is protected. Prior to any Write operation, the

Write-Enable (WREN) instruction must be executed. CE#

must remain active low for the duration of the Chip-Erase

instruction sequence. The Chip-Erase instruction is initiated

by executing an 8-bit command, 60H or C7H. CE# must be

driven high before the instruction is executed. The user may

poll the Busy bit in the software status register or wait TCE

for the completion of the internal self-timed Chip-Erase

cycle. See Figure 17 for the Chip-Erase sequence.

FIGURE 17: Chip-Erase Sequence

CE#

SCK

ADDR

01 2 3 4 5 6 7 8

ADDR

HIGH IMPEDANCE

15 16

23 24

MODE 0

MODE 3

1203 F15.0

MSB

CE#

SCK

01 2 3 4 5 6 7

60 or C7

HIGH IMPEDANCE

MODE 0

MODE 3

1203 F16.0

MSB

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