TPS53129

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SLVSAE6B – OCTOBER 2009 – REVISED JULY 2010

LAYOUT SUGGESTIONS

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Keep the input switching current loop as small as possible.

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Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also be kept

as small as possible.

•

Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and

inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the

feedback pin (FBx) of the device.

•

Keep analog and non-switching components away from switching components.

•

Make a single point connection from the signal ground to power ground.

•

Do not allow switching current to flow under the device.

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