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SC4612HSTRT Datasheet(PDF) 10 Page - Semtech Corporation |
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SC4612HSTRT Datasheet(HTML) 10 Page - Semtech Corporation |
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10 / 18 page  SC4612H 0 Applications Information (continued) Over Current Protection The SC462H features low side MOSFET RDS(ON) current sensing and hiccup mode over current protection. The voltage across the bottom FET is sampled approximately 50ns after it is turned on to prevent false tripping due to ringing of the phase node. The internally set over current threshold is 00mV typical. This can be adjusted up or down by connecting a resistor between ILIM and DRV or GND respectively. When programming with an external resistor,thresholdsetpointaccuracywillbedegraded to 30%. The FET R DS(ON) at temperature will typically be 50% or more of the room temperature value. Allowance should be made for these sources of error when programming a threshold value. When an over current event occurs, the SC462H immediately disables both gate drives. The SS ramp continues to its final value, if not already there. Once at final value, the SS capacitor is discharged at approximately uA until SS low value is reached (approx 0.8V). The SS/ Hiccup cycle will then repeat until the fault condition is removed and the SC462H starts up normally on the next SS cycle. Gate Drive/Control The SC462H provides integrated high current drivers for fast switching of large MOSFETs. The higher gate current will reduce switching losses of the larger MOSFETs. The low side gate drive is supplied directly from the DRV. The high side gate drive is bootstraped from the DRV pin. Cross conduction prevention circuitry ensures a non overlapping (30ns typical) gate drive between the top and bottom MOSFETs. This prevents shoot through losses which provides higher efficiency. Typical total minimum off time for the SC462H is about 30ns. Error Amplifer Design The SC462H is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate the output voltage. The power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below. . . . . . . . . . (2) e capacitanc Output C resistance Load R voltage ramp peak to Peak V ESR capacitor Output R inductance Output L voltage Input V , where LC s R L s 1 sCR 1 V V ) s ( G L R ESR IN 2 L ESR R IN VD = = = = = = + + + = The classical Type III compensation network can be built around the error amplifier as shown below: Fig 1. Type III compensation network The transfer function of the compensation network is as follows: . . . . . . . . . (3) ( ) ( ) + = ω = ω + = ω + = ω = ω ω + ω + ω + ω + ⋅ ω = 3 1 3 1 2 2 P 2 3 1 P 3 1 1 1 2 3 1 2 Z 1 2 1 Z 2 P 1 P 2 Z 1 Z 1 COMP C C C C R 1 C R 1 , C C R 1 C R R 1 , C R 1 , where s 1 s 1 s 1 s 1 s ) s ( G The design guidelines are as following: . Set the loop gain crossover frequency w C for given switching frequency. 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select w Z and wZ2 such that they are placed near w O to dampen peaking; the loop gain should cross |
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