EP3C5 datasheet(30/34 Pages) ALTERA

30 / 34 page

1–30

Chapter 1: Cyclone III Device Data Sheet

Glossary

Cyclone III Device Handbook, Volume 2

Altera Corporation

High-speed receiver/transmitter input and output clock period.

TCCS (Channel-

to-channel-skew)

HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,

including t

CO variation and clock skew. The clock is included in the TCCS measurement.

tcin

Delay from clock pad to I/O input register.

Delay from clock pad to I/O output.

tcout

Delay from clock pad to I/O output register.

DUTY

HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.

FA LL

Signal High-to-low transition time (80–20%).

Input register hold time.

Timing Unit

Interval (TUI)

HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data

sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t

C /w).

INJITTER

Period jitter on PLL clock input.

OUTJITTER_DEDC LK

Period jitter on dedicated clock output driven by a PLL.

OUTJITTER_IO

Period jitter on general purpose I/O driven by a PLL.

tpllcin

Delay from PLL inclk pad to I/O input register.

tpllcout

Delay from PLL inclk pad to I/O output register.

Transmitter

Output Waveform

Transmitter Output Waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O

Standards

RISE

Signal Low-to-high transition time (20–80%).

Input register setup time.

——

Table 1–39. Glossary (Part 4 of 5)

Letter

Term

Definitions

Single-Ended Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

Positive Channel (p) = V

Negative Channel (n) = V

Ground

VOD

0 V

Vos

- n

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