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LM5109ASD Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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LM5109ASD Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 9 page ![]() Switching Characteristics Specifications in standard typeface are for T J = +25˚C, and those in boldface type apply over the full operating junction tem- perature range. Unless otherwise specified, V DD =VHB = 12V, VSS =VHS = 0V, No Load on LO or HO. Symbol Parameter Conditions Min Typ Max Units LM5109A t LPHL Lower Turn-Off Propagation Delay (LI Falling to LO Falling) 30 56 ns t HPHL Upper Turn-Off Propagation Delay (HI Falling to HO Falling) 30 56 ns t LPLH Lower Turn-On Propagation Delay (LI Rising to LO Rising) 32 56 ns t HPLH Upper Turn-On Propagation Delay (HI Rising to HO Rising) 32 56 ns t MON Delay Matching: Lower Turn-On and Upper Turn-Off 2 15 ns t MOFF Delay Matching: Lower Turn-Off and Upper Turn-On 2 15 ns t RC,tFC Either Output Rise/Fall Time C L = 1000 pF 15 - ns t PW Minimum Input Pulse Width that Changes the Output 50 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5k Ω resistor into each pin. Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions. Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not exceed -5V. www.national.com 4 |
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