DS2156L datasheet(4/265 Pages) MAXIM

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DS2156

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22.6

D4/SLC-96 OPERATION .......................................................................................................... 149

23.

LINE INTERFACE UNIT (LIU) ..................................................................................... 150

23.1

LIU OPERATION ...................................................................................................................... 150

23.2

RECEIVER ............................................................................................................................... 150

23.2.1

Receive Level Indicator and Threshold Interrupt ...............................................................................151

23.2.2

Receive G.703 Synchronization Signal (E1 Mode)............................................................................151

23.2.3

Monitor Mode .....................................................................................................................................151

23.3

TRANSMITTER.......................................................................................................................... 152

23.3.1

Transmit Short-Circuit Detector/Limiter..............................................................................................152

23.3.2

Transmit Open-Circuit Detector .........................................................................................................152

23.3.3

Transmit BPV Error Insertion .............................................................................................................152

23.3.4

Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................152

23.4

MCLK PRESCALER.................................................................................................................. 153

23.5

JITTER ATTENUATOR ............................................................................................................... 153

23.6

CMI (CODE MARK INVERSION) OPTION .................................................................................... 153

23.7

LIU CONTROL REGISTERS ....................................................................................................... 154

23.8

RECOMMENDED CIRCUITS........................................................................................................ 161

23.9

COMPONENT SPECIFICATIONS.................................................................................................. 163

24.

UTOPIA BACKPLANE INTERFACE........................................................................... 168

24.1

DESCRIPTION .......................................................................................................................... 168

24.1.1

List of Applicable Standards ..............................................................................................................168

24.1.2

Acronyms and Definitions ..................................................................................................................168

24.2

UTOPIA CLOCK MODES.......................................................................................................... 169

24.3

FULL T1/E1 MODE AND CLEAR-CHANNEL E1 MODE ................................................................. 169

24.4

FRACTIONAL T1/E1 MODE........................................................................................................ 170

24.5

TRANSMIT OPERATION............................................................................................................. 171

24.5.1

UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV.......................................................171

24.5.2

UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV) ...................................................174

24.5.3

Transmit Processing ..........................................................................................................................176

24.6

RECEIVE OPERATION............................................................................................................... 177

24.6.1

Receive Processing ...........................................................................................................................177

24.6.2

UTOPIA Side Receive: Muxed Mode with One Receive CLAV.........................................................179

24.6.3

UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV) .....................................................180

24.7

REGISTER DEFINITIONS ........................................................................................................... 182

24.8

RECEIVE FIFO OVERRUN ........................................................................................................ 193

24.9

UTOPIA DIAGNOSTIC LOOPBACK ............................................................................................ 193

25.

PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ........ 194

26.

BERT FUNCTION ........................................................................................................ 201

26.1

STATUS................................................................................................................................... 201

26.2

MAPPING................................................................................................................................. 201

26.3

BERT REGISTER DESCRIPTIONS ............................................................................................. 203

26.4

BERT REPETITIVE PATTERN SET............................................................................................. 207

26.5

BERT BIT COUNTER ............................................................................................................... 208

26.6

BERT ERROR COUNTER ......................................................................................................... 209

27.

PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................ 211

27.1

NUMBER-OF-ERRORS REGISTERS ............................................................................................ 213

27.1.1

Number-of-Errors Left Register..........................................................................................................214

28.

INTERLEAVED PCM BUS OPERATION (IBO)........................................................... 215

28.1

CHANNEL INTERLEAVE ............................................................................................................. 215

28.2

FRAME INTERLEAVE ................................................................................................................. 215

29.

EXTENDED SYSTEM INFORMATION BUS (ESIB).................................................... 218

30.

PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER....................................... 222

31.

FRACTIONAL T1/E1 SUPPORT ................................................................................. 222

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