DS2156L datasheet(6/265 Pages) MAXIM

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DS2156

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LIST OF FIGURES

Figure 2-1. Block Diagram........................................................................................................................14

Figure 2-2. Receive and Transmit LIU (TDM Backplane Enabled)...........................................................15

Figure 2-3. Receive and Transmit LIU (UTOPIA Backplane Enabled) .....................................................16

Figure 2-4. Receive and Transmit Framer/HDLC .....................................................................................17

Figure 2-5. Backplane Interface (TDM Backplane Enabled) ....................................................................18

Figure 2-6. Backplane Interface (UTOPIA Bus Enabled) .........................................................................19

Figure 3-1. 10mm CSBGA Pin Configuration (TDM Signals Shown) .......................................................38

Figure 6-1. Programming Sequence ........................................................................................................48

Figure 7-1. Clock Map (TDM Mode) .........................................................................................................52

Figure 15-1. Simplified Diagram of Receive Signaling Path.....................................................................90

Figure 15-2. Simplified Diagram of Transmit Signaling Path....................................................................96

Figure 19-1. CRC-4 Recalculate Method ...............................................................................................116

Figure 23-1. Typical Monitor Application ................................................................................................151

Figure 23-2. CMI Coding ........................................................................................................................153

Figure 23-3. Basic Interface ...................................................................................................................161

Figure 23-4. Protected Interface Using Internal Receive Termination....................................................162

Figure 23-5. E1 Transmit Pulse Template..............................................................................................164

Figure 23-6. T1 Transmit Pulse Template ..............................................................................................164

Figure 23-7. Jitter Tolerance ..................................................................................................................165

Figure 23-8. Jitter Tolerance (E1 Mode).................................................................................................165

Figure 23-9. Jitter Attenuation (T1 Mode)...............................................................................................166

Figure 23-10. Jitter Attenuation (E1 Mode) ............................................................................................166

Figure 23-11. Optional Crystal Connections...........................................................................................167

Figure 24-1. UTOPIA Clocking Configurations.......................................................................................169

Figure 24-2. Polling Phase and Selection Phase at Transmit Interface .................................................172

Figure 24-3. End and Restart of Cell at Transmit Interface ...................................................................173

Figure 24-4. Transmission to PHY Paused for Three Cycles .................................................................174

Figure 24-5. Example of Direct Status Indication, Transmit Direction ....................................................175

Figure 24-6. Transmit Cell Flow .............................................................................................................176

Figure 24-7. Cell-Delineation State Diagram..........................................................................................177

Figure 24-8. Header Correction State Machine......................................................................................178

Figure 24-9. Polling Phase and Selection at Receive Interface..............................................................179

Figure 24-10. End and Restart of Cell Transmission at Receive Interface.............................................180

Figure 24-11. Example of Direct Status Indication, Receive Direction ...................................................181

Figure 26-1. Simplified Diagram of BERT in Network Direction .............................................................202

Figure 26-2. Simplified Diagram of BERT in Backplane Direction..........................................................202

Figure 28-1. IBO Example ......................................................................................................................217

Figure 29-1. ESIB Group of Four DS2156s............................................................................................218

Figure 33-1. JTAG Functional Block Diagram ........................................................................................225

Figure 33-2. TAP Controller State Diagram............................................................................................228

Figure 34-1. Receive-Side D4 Timing ....................................................................................................234

Figure 34-2. Receive-Side ESF Timing ..................................................................................................234

Figure 34-3. Receive-Side Boundary Timing (with elastic store disabled) .............................................235

Figure 34-4. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ...........................235

Figure 34-5. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ...........................236

Figure 34-6. Transmit-Side D4 Timing ...................................................................................................236

Figure 34-7. Transmit-Side ESF Timing .................................................................................................237

Figure 34-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)...........................................237

Figure 34-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ..........................238

Figure 34-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ........................238

Figure 34-11. Receive-Side Timing ........................................................................................................239

Figure 34-12. Receive-Side Boundary Timing (with Elastic Store Disabled)..........................................239

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