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TDA19977AHV Datasheet(PDF) 21 Page - NXP Semiconductors |
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TDA19977AHV Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 40 page  TDA19977A_TDA19977B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 19 November 2010 21 of 40 NXP Semiconductors TDA19977A; TDA19977B Triple input HDMI receiver interface with digital processing 13. Output video port formats [1] Z = high-impedance; L = LOW-level; depending on bit VPL. Table 11. Output in 12-bit video port format (register VP_CTRL address = 21h) Signal YCbCr 4:2:2 semi-planar[1] YCbCr 4:2:2 ITU-R BT.656[1] VP[29] Y0[11] Y1[11] Z/L Z/L Z/L Z/L VP[28] Y0[10] Y1[10] Z/L Z/L Z/L Z/L VP[27] Y0[9] Y1[9] Z/L Z/L Z/L Z/L VP[26] Y0[8] Y1[8] Z/L Z/L Z/L Z/L VP[25] Y0[7] Y1[7] Z/L Z/L Z/L Z/L VP[24] Y0[6] Y1[6] Z/L Z/L Z/L Z/L VP[23] Y0[5] Y1[5] Z/L Z/L Z/L Z/L VP[22] Y0[4] Y1[4] Z/L Z/L Z/L Z/L VP[21] Y0[3] Y1[3] Z/L Z/L Z/L Z/L VP[20] Y0[2] Y1[2] Z/L Z/L Z/L Z/L VP[19] Y0[1] Y1[1] Z/L Z/L Z/L Z/L VP[18] Y0[0] Y1[0] Z/L Z/L Z/L Z/L VP[17] Cb[11] Cr[11] Cb[11] Y0[11] Cr[11] Y1[11] VP[16] Cb[10] Cr[10] Cb[10] Y0[10] Cr[10] Y1[10] VP[15] Cb[9] Cr[9] Cb[9] Y0[9] Cr[9] Y1[9] VP[14] Cb[8] Cr[8] Cb[8] Y0[8] Cr[8] Y1[8] VP[13] Cb[7] Cr[7] Cb[7] Y0[7] Cr[7] Y1[7] VP[12] Cb[6] Cr[6] Cb[6] Y0[6] Cr[6] Y1[6] VP[11] Cb[5] Cr[5] Cb[5] Y0[5] Cr[5] Y1[5] VP[10] Cb[4] Cr[4] Cb[4] Y0[4] Cr[4] Y1[4] VP[9] Cb[3] Cr[3] Cb[3] Y0[3] Cr[3] Y1[3] VP[8] Cb[2] Cr[2] Cb[2] Y0[2] Cr[2] Y1[2] VP[7] Cb[1] Cr[1] Cb[1] Y0[1] Cr[1] Y1[1] VP[6] Cb[0] Cr[0] Cb[0] Y0[0] Cr[0] Y1[0] VP[5] Z/LZ/L Z/LZ/L Z/L Z/L VP[4] Z/LZ/L Z/LZ/L Z/L Z/L VP[3] Z/LZ/L Z/LZ/L Z/L Z/L VP[2] Z/LZ/L Z/LZ/L Z/L Z/L VP[1] Z/LZ/L Z/LZ/L Z/L Z/L VP[0] Z/LZ/L Z/LZ/L Z/L Z/L |
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