82573 datasheet(21/39 Pages) INTEL

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Datasheet—82573

3.3.4

Internal LVR Power Sequencing

All supplies should rise monotonically. Sequencing of the supplies is controlled by the

82573.

3.3.4.1

Power Up Sequencing and Tracking

During power up, the sequencing and tracking of the internally controlled supplies

(2.5V and 1.2V) are controlled by the 82573. No specific motherboard requirements

are necessary to prevent electrical overstress or latch-up.

The 82573 analog voltage (2.5V) never exceeds the 3.3V supply at any time during the

power up. This is because the 2.5V supply is generated from the 3.3V supply when the

internal voltage regulator control logic is being used. Figure 3 shows the internal LVR

circuit. The 2.5V supply tracks the 3.3V ramp.

The 82573 core voltage (1.2V) never exceeds the 3.3V at any time during the power

up. This is because the 2.5V supply is generated from the 3.3V supply when the

internal voltage regulator control logic is being used. Figure 3 shows the internal LVR

circuit. The 1.2V ramp is delayed internally to prevent it from exceeding the 2.5V and

3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.

The delay is approximated by Tramp(3.3V)*0.25 < Tdelay(1.2V) < Tramp(3.3V)*0.75.

Tramp is defined to the ramp rate of the 3.3V input to the internal voltage regulator

circuit.

• It is recommended that the voltage on a lower voltage rail never exceed the

voltage on a higher voltage rail during power on.

• There are no minimum time requirements between the voltage rails as long as they

power up in sequence: 3.3V → 2.5V → 1.2V.

• All 3 supplies must be stable for at least 80 ms before LAN_PWR_GOOD is

asserted. 100 ms is preferable if possible.

• A PCIe* reset must occur after LAN Power Good is active.

3.3.4.2

Internal LVR Power Down Sequencing

There are no specific power down sequencing and tracking requirements for the 82573

device. The risk of latch-up or electrical overstress is small because the only charge

storing in decoupling capacitors is left in the system.

Figure 3.

Power Supply Sequencing

Voltage

1.2V

2.5V

3.3V

Minimum 80 ms

Time

LAN_PWR_GOOD

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