QX6000 datasheet(63/98 Pages) INTEL

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Datasheet

Land Listing and Signal Descriptions

BPM[5:0]#

BPMb[3:0]#

Input/

Output

BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint

and performance monitor signals. They are outputs from the

processor which indicate the status of breakpoints and

programmable counters used for monitoring processor

performance. BPM[5:0]# and BPMb[3:0]# should connect the

appropriate pins/lands of all processor FSB agents. BPM[3:0]# are

associated with core 0. BPMb[3:0]# are associated with core 1.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP

port. PRDY# is a processor output used by debug tools to determine

processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP

port. PREQ# is used by debug tools to request debug operation of

the processor.

These signals do not have on-die termination. Refer to Section 2.5.2

for termination requirements.

BPRI#

Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the processor FSB. It must connect the appropriate pins/lands of all

processor FSB agents. Observing BPRI# active (as asserted by the

priority agent) causes all other agents to stop issuing new requests,

unless such requests are part of an ongoing locked operation. The

priority agent keeps BPRI# asserted until all of its requests are

completed, then releases the bus by de-asserting BPRI#.

BR0#

Input/

Output

BR0# drives the BREQ0# signal in the system and is used by the

processor to request the bus. During power-on configuration this

signal is sampled to determine the agent ID = 0.

This signal does not have on-die termination and must be

terminated.

BSEL[2:0]

Output

The BCLK[1:0] frequency select signals BSEL[2:0] are used to

select the processor input clock frequency. Table 16 defines the

possible combinations of the signals and the frequency associated

with each combination. The required frequency is determined by the

processor, chipset and clock synthesizer. All agents must operate at

the same frequency. For more information about these signals,

including termination recommendations refer to Section 2.7.2.

COMP8

COMP[3:0]

Analog

COMP[3:0] and COMP8 must be terminated to VSS on the system

board using precision resistors.

Table 25.

Signal Description (Sheet 2 of 9)

Name

Type

Description

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