T7200 datasheet(13/91 Pages) INTEL

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Datasheet

Low Power Features

2.1.1

Core Low Power State Descriptions

2.1.1.1

Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2

Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when a core executes the HALT instruction.

The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,

LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to

immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Intel®

Architectures Software Developer's Manual, Volume 3A/3B: System Programmer's

Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

Figure 2.

Package Low Power States

Table 1.

Coordination of Core Low Power States at the Package Level

Package State

Core1 State

Core0 State

C1/Auto

HALT/

MWAIT

Normal

C1/AutoHALT/

MWAIT

Normal

Stop-Grant

Normal

Stop-Grant

Deep Sleep

Normal

Stop-Grant

Deep Sleep

Deeper Sleep/

Intel®

Enhanced

Deeper Sleep

Stop

Grant

Snoop

Normal

Stop

Grant

Deep

Sleep

STPCLK# asserted

Snoop

serviced

Snoop

occurs

Deeper

Sleep

†

Sleep

SLP# asserted

SLP# de-asserted

DPSLP# asserted

DPSLP# de-asserted

DPRSTP# de-asserted

DPRSTP# asserted

STPCLK# de-asserted

† — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state.

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