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T8100 Datasheet(PDF) 13 Page - Intel Corporation

Part # T8100
Description  Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process
PDF  77 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

T8100 Datasheet(HTML) 13 Page - Intel Corporation

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13
Low Power Features
NOTES:
1.
AutoHALT or MWAIT/C1.
2.1.1
Core Low-Power State Descriptions
2.1.1.1
Core C0 State
This is the normal operating state for cores in the processor.
2.1.1.2
Core C1/AutoHALT Power-Down State
C1/AutoHALT is a low-power state entered when a core executes the HALT instruction.
The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to
immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT power-down state. See the Intel® 64 and IA-32 Architectures
Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more
information.
The system can generate a STPCLK# while the processor is in the AutoHALT power-
down state. When the system deasserts the STPCLK# interrupt, the processor will
return execution to the HALT state.
Figure 2.
Package Low-Power States
Table 1.
Coordination of Core Low-Power States at the Package Level
Package State
Core 1 State
Core 0 State
C0C1C2C3
C4/C6
C0
Normal
Normal
Normal
Normal
Normal
C11
Normal
Normal
Normal
Normal
Normal
C2
Normal
Normal
Stop-Grant
Stop-Grant
Stop-Grant
C3
Normal
Normal
Stop-Grant
Deep Sleep
Deep Sleep
C4/C6
Normal
Normal
Stop-Grant
Deep Sleep
Deeper Sleep/Intel®
Enhanced Deeper Sleep/
Intel® Deep Power-Down
Stop
Grant
Snoop
Normal
Stop
Grant
Deep
Sleep
STPCLK# asserted
Snoop
serviced
Snoop
occurs
Deeper
Sleep
†
Sleep
SLP# asserted
SLP# de-asserted
DPSLP# asserted
DPSLP# de-asserted
DPRSTP# de-asserted
DPRSTP# asserted
STPCLK# de-asserted
† — Deeper Sleep includes the Deeper Sleep state, Intel Enhanced Deeper Sleep state, and C6 state



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