T8100 datasheet(21/77 Pages) INTEL

21 / 77 page

Datasheet

Low Power Features

Extended Stop-Grant and Enhanced Deeper Sleep must be enabled via the

BIOS for the processor to remain within specification. Any attempt to operate the

processor outside these operating limits may result in permanent damage to the

processor. As processor technology changes, enabling the extended low-power states

becomes increasingly crucial when building computer systems. Maintaining the proper

BIOS configuration is key to reliable, long-term system operation. Not complying to this

guideline may affect the long-term reliability of the processor.

Caution:

Enhanced Intel SpeedStep Technology transitions are multi-step processes that require

clocked control. These transitions cannot occur when the processor is in the Sleep or

Deep Sleep package low-power states since processor clocks are not active in these

states. Extended Deeper Sleep is an exception to this rule when the Hard C4E

configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep

state configuration will lower core voltage to the Deeper Sleep level while in Deeper

Sleep and, upon exit, will automatically transition to the lowest operating voltage and

frequency to reduce snoop service latency. The transition to the lowest operating point

or back to the original software requested point may not be instantaneous.

Furthermore, upon very frequent transitions between active and idle states, the

transitions may lag behind the idle state entry resulting in the processor either

executing for a longer time at the lowest operating point or running idle at a high

operating point. Observations and analyses show this behavior should not significantly

impact total power savings or performance score while providing power benefits in

most other cases.

2.4

FSB Low-Power Enhancements

The processor incorporates FSB low-power enhancements:

• Dynamic FSB Power-Down

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On-Die Termination disabling

•Low VCCP (I/O termination voltage)

• Dynamic FSB frequency switching

The processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates

them only when data bus activity occurs, resulting in significant power savings with no

performance impact. BPRI# control also allows the processor address and control input

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows

a reciprocal power reduction in chipset address and control input buffers when the

processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers

is disabled when the signals are driven low, resulting in additional power savings. The

low I/O termination voltage is on a dedicated voltage plane independent of the core

voltage, enabling low I/O switching power at all times.

2.4.1

Dynamic FSB Frequency Switching

Dynamic FSB frequency switching effectively reduces the internal bus clock frequency

in half to further decrease the minimum processor operating frequency from the

Enhanced Intel SpeedStep Technology performance states and achieve the Super Low

Frequency Mode (SuperLFM). This feature is supported at FSB frequencies of 800-MHz

on the Santa Rosa platform and does not entail a change in the external bus signal

(BCLK) frequency. Instead, both the processor and (G)MCH internally lower their BCLK

reference frequency to 50% of the externally visible frequency. Both the processor and

(G)MCH maintain a virtual BCLK signal (“VBCLK”) that is aligned to the external BCLK,

T8100 Datasheet(PDF) 21 Page - Intel Corporation

T8100 Datasheet(HTML) 21 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL