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MAX8686 Datasheet(PDF) 21 Page - Maxim Integrated Products |
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MAX8686 Datasheet(HTML) 21 Page - Maxim Integrated Products |
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21 / 23 page ![]() Single/Multiphase, Step-Down, DC-DC Converter Delivers Up to 25A Per Phase ______________________________________________________________________________________ 21 be less than or equal to 1/5 the switching frequency. Select a value for fC in the range: The feedback voltage-divider gain (VREF/VOUT) should be included for an output voltage higher than 3.3V, where VREFIN is equal to 3.3V. At the crossover frequency, the total loop gain must equal 1, and is expressed as: For the case where fzMOD is greater than fC: Then RC can be calculated as: where gmEA = 1.7mS. The error-amplifier compensation zero formed by RC and CC should be set at the modulator pole fPMOD. Calculate the value of CC as follows: If fPMOD is less than 5 x fC, add a second capacitor CF from COMP to GND. The value of CF is: As the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. For the case where fzMOD is less than fC: The power modulator gain at fC is: The error-amplifier gain at fC is: RC is calculated as: where gmEA = 1.7mS. CC is calculated from: CF is calculated from: The current-mode control model on which the above design procedure is based requires an additional high- frequency term, GS(s), to account for the effect of sam- pling the peak inductor current. The term GS(s) produces additional phase lag at crossover and should be modeled to estimate the phase margin obtainable by the selected compensation components. As a final step, it is useful to plot the dB gain and phase of the following loop-gain transfer function and check the obtained phase margin. A phase margin of at least 45° is recommended: where the sampling effect quality factor is: Q KD C S = ×× − − [] 1 10 5 π (( ) . ) Gs s Qf s f S cSW SW () = + ×× + × () ⎛ ⎝ ⎜ ⎜ ⎞ ⎠ ⎟ ⎟ 1 1 2 2 π π Gs Rg R Lf Ks D LOOP LOAD MC LOAD SW () () = × + × ×× − ()− 11 0 05 12 12 . (/ ) (/ ) ⎡⎣ ⎤⎦ ⎡ ⎣ ⎢ ⎤ ⎦ ⎥ × +× +× sf sf zMOD pMOD π π ×× +× +× × + × (/ ) (/ ) ( / ) 12 12 12 sf sf sf zEA pEA pdEA π ππ ×× ×× gRo V V G mEA REFIN OUT S ( C Rf F CzMOD = ×× 1 2 π C fR C pMOD C = ×× 1 2 π R V V f gG f C OUT FB C mEA MOD fc zMOD =× ×× () Gg R f f EA fc mEA C zMOD C () =× × GG f f MOD fc MOD dc pMOD zMOD () ( ) =× C Rf F CzMOD = ×× 1 2 π C fR C pMOD C = ×× 1 2 π R V gV G C OUT mEA REFIN MOD fc = ×× () Gg R GG f f EA fc mEA C MOD fc MOD dc pMOD C () () ( ) =× =× GG V V EA fc MOD fc REFIN OUT () () ×× = 1 ff f pMOD C SW << ≤ 5 |
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