R29 datasheet(156/473 Pages) RENESAS

156 / 473 page

R8C/28 Group, R8C/29 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 137 of 441

REJ09B0279-0210

Figure 14.2

Registers TRACR and TRAIOC

Timer RA Control Register

(4)

Symbol

Address

After Reset

TRACR

0100h

00h

Bit Symbol

Bit Name

Function

NOTES:

5. Set to 0 in timer mode, pulse output mode, and event counter mode.

TUNDF

When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TRAPRE and TRA are set to the values after a

reset.

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Refer to 14.1.6 Notes on Tim er RA for precautions regarding bits TSTART and TCSTF.

Timer RA count start bit(1)

Timer RA count forcible stop

bit(2)

Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains

unchanged w hen 1 is w ritten.

In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR

—

(b7-b6)

—

TEDGF

0 : Active edge not received

1 : Active edge received

(end of measurement period)

b7 b6 b5 b4 b3 b2

When this bit is set to 1, the count is forcibly

stopped. When read, its content is 0.

—

(b3)

b1 b0

Active edge judgment

flag(3, 5)

Timer RA underflow flag(3, 5) 0 : No underflow

1 : Underflow

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

TCSTF

TSTART

0 : Count stops

1 : During count

0 : Count stops

1 : Count starts

Timer RA count status flag(1)

TSTOP

Timer RA I/O Control Register

Symbol

Address

After Reset

TRAIOC

0101h

00h

Bit Symbol

Bit Name

Function

INT1

_____

/TRAIO select bit

TIPF0

TOENA

TRAIO input filter select bits

TIPF1

Function varies depending on operating mode.

TRAIO output control bit

TRAO output enable bit

—

TEDGSEL

TOPCR

TRAIO polarity sw itch bit

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

(b7-b6)

b7 b6 b5 b4 b3 b2

TIOSEL

b1 b0

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