R29 datasheet(158/473 Pages) RENESAS

158 / 473 page

R8C/28 Group, R8C/29 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 139 of 441

REJ09B0279-0210

14.1.1

Timer Mode

In this mode, the timer counts an internally generated count source (refer to Table 14.2 Specifications of

Timer Mode).

Figure 14.4 shows the TRAIOC Register in Timer Mode.

NOTE:

1. For J, K version, fC32 cannot be selected.

Figure 14.4

TRAIOC Register in Timer Mode

Table 14.2

Specifications of Timer Mode

Item

Specification

Count sources

f1, f2, f8, fOCO, fC32(1)

Count operations

• Decrement

• When the timer underflows, the contents of the reload register are reloaded

and the count is continued.

Divide ratio

1/(n+1)(m+1)

n: Value set in TRAPRE register, m: Value set in TRA register

Count start condition

1 (count starts) is written to the TSTART bit in the TRACR register.

Count stop conditions

• 0 (count stops) is written to the TSTART bit in the TRACR register.

• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.

Interrupt request

generation timing

When timer RA underflows [timer RA interrupt].

INT1/TRAIO pin function Programmable I/O port, or INT1 interrupt input

TRAO pin function

Programmable I/O port

Read from timer

The count value can be read by reading registers TRA and TRAPRE.

Write to timer

• When registers TRAPRE and TRA are written while the count is stopped,

values are written to both the reload register and counter.

• When registers TRAPRE and TRA are written during the count, values are

written to the reload register and counter (refer to 14.1.1.1 Timer Write

Control during Count Operation).

Timer RA I/O Control Register

Symbol

Address

After Reset

TRAIOC

0101h

00h

Bit Symbol

Bit Name

Function

INT1

_____

/TRAIO select bit

0 : INT1

_____

/TRAIO pin (P1_7)

1 : INT1

_____

/TRAIO pin (P1_5)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

TRAO output enable bit

TRAIO input filter select bits

Set to 0 in timer mode.

TRAIO polarity sw itch bit

Set to 0 in timer mode.

TRAIO output control bit

—

(b7-b6)

—

TOPCR

TOENA

TIPF0

TIPF1

b7 b6 b5 b4 b3 b2

TIOSEL

b1 b0

TEDGSEL

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