LM3450 datasheet(16/28 Pages) NSC

16 / 28 page

PHASE DIMMER OPERATION

A simplified schematic of a phase dimmer is shown in Figure

8. An RC network consisting of R1, R2, and C1 delay the turn-

on of the triac until the voltage on C1 reaches the trigger

voltage of the diac. Increasing the resistance of the poten-

tiometer (wiper moving downward) increases the turn-on de-

lay which decreases the on-time or “conduction angle” of the

triac (

θ). This reduces the average power delivered to the

load.

30127429

FIGURE 8. Basic Forward Phase Dimmer

Phase dimmer voltage waveforms are shown in Figure 9.

Figure 9a shows the full sinusoid of the input voltage. Even

when set to full brightness; few dimmers will provide 100%

conduction angle.

Figure 9b shows a waveform from a forward phase dimmer.

The off-time can be referred to as the firing angle and is simply

180° –

θ.

Figure 9c shows the waveform of a reverse phase dimmer

(also called an electronic dimmer in the lighting industry).

These typically or more expensive, microcontroller based

dimmers that use switching devices other than triacs. Note

that the conduction angle starts from the zero-crossing, and

terminates some time later. This method of control reduces

the noise spike at the transition.

Any form of phase dimming modulates the incoming AC

waveform by chopping part of the sinusoid, reducing the av-

erage power to the load. These dimmers work very well with

standard incandescent bulbs, but not with power converters.

A converter attempts to regulate the load in with presence of

any input, effectively ignoring the phase angle. To implement

a dimmable converter, the angle must be sensed at the input,

decoded and used to properly control the LED current regu-

lator.

30127430

FIGURE 9. Phase Dimming Waveforms

PRECISION VOLTAGE REFERENCE

The LM3450 provides a 3V voltage reference (V

REF) for bi-

asing the V

ADJ pin as well as any external circuitry. VREF is

regulated once V

CC exceeds 3V. There is a 2mA current limit

for the reference. A 10nF ceramic bypass capacitor should be

placed from V

REF to GND.

LOW POWER SHUTDOWN

The LM3450 can be placed into a low power shutdown by

grounding the V

ADJ pin (any voltage below 75mV). During low

power shutdown, the device will turn on the GATE for one

cycle followed by a fixed off-time of 42µs and the cycle re-

peats. During shutdown, the DIM output will be high (zero light

output) since the buffer rail at FLT1 will be at or near zero.

This feature is designed to hold up the PFC output voltage

while removing the load (turning the LEDs off).

THERMAL SHUTDOWN

Internal thermal shutdown circuitry is provided to protect the

IC in the event that the maximum junction temperature is ex-

ceeded. The threshold for thermal shutdown is 160°C with a

20°C hysteresis. During thermal shutdown GATE is disabled.

LM3450 Datasheet(PDF) 16 Page - National Semiconductor (TI)

LM3450 Datasheet(HTML) 16 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL