FX589P datasheet(9/18 Pages) CMLMICRO

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Application Information ......

Tx Signal Path Description

The binary data applied to the ‘Tx Data’ input is

re-timed within the chip on each rising edge of the ‘Tx

Clock’ and then converted to a 1 Volt peak-to-peak

binary signal centred about V

BIAS (for VDD = 5.0 V).

If the ‘Tx Enable’ input is ‘high,’ then this internal

binary signal will be connected to the input of the

lowpass Tx Filter, and the output of the filter connected

to the ‘Tx Out’ pin.

Tx Enable

Tx Filter Input

Tx Out Pin

“1” (high)

VDD/

Volt p-p Data

Filtered Data

“0” (low)

BIAS

BIAS via 500kΩ

Fig.8 Rx and Tx Clock Data Timings

A ‘low’ input to the ‘Tx Enable’ will connect the input of

the Tx Filter to V

BIAS, and disconnect the ‘Tx Out’ pin

from the filter, connecting it instead to V

BIAS through a

high resistance (nominally 500k

Ω).

The Tx Filter has a lowpass frequency response,

which is approximately gaussian in shape as shown in

Figure 9, to minimise amplitude and phase distortion of

the binary signal while providing sufficient attenuation

of the high frequency-components which would

otherwise cause interference into adjacent radio

channels. The actual filter bandwidth to be used in any

particular application will be determined by the overall

system requirements. The attenuation-vs-frequency

response of the transmit filtering provided by the

FX589 have been designed to meet the specifications

for most GMSK modem systems, having a -3dB

bandwidth switchable between 0.3 and 0.5 times the

data bit-rate (BT).

Note that an external RC network is required

between the ‘Tx Out’ pin and the input to the

Frequency Modulator (see Figures 2 and 3). This

network, which can form part of any dc level shifting

and gain adjustment circuitry, forms an important part

of the transmit signal filtering, and the ground

connection to the capacitor C

1 should be positioned to

give maximum attenuation of high-frequency noise into

the modulator.

The signal at ‘Tx Out’ is centred around V

BIAS, going

positive for logic “1” (high) level inputs to the ‘Tx Data’

input and negative for logic “0” (low) inputs.

When the transmit circuits are put into a

‘powersave’ mode (by a logic “1” to the ‘Tx PS’ pin) the

output voltage of the Tx Filter will be undefined.

When power is subsequently restored to the Tx

Filter, its output will take several bit-times to settle. The

‘Tx Enable’ input can be used to prevent these

abnormal voltages from appearing at the ‘Tx Out’ pin.

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