LA7577 datasheet(13/16 Pages) SANYO

13 / 16 page

LA7577N

No. 4037—13/16

Equalization Ampliﬁer (Pins 19 to 21)

The video signal, after passing through the 4.5MHz trap, is

input on pin 19 to the equalization ampliﬁer, and output on

pin 21. A resistor should be connected between the emit-

ter-follower output and ground to ensure adequate output

drive capability. The resistor should be

≥2.7kΩ (V

CC =

12V) or

≥2.2kΩ (V

CC = 9V). A buffer transistor should be

used if the signal is taken off-board.

Equalization ampliﬁer design

The equalization ampliﬁer has an external series resonant

circuit, shown in Figure 24, which controls the frequency

characteristic. The output voltage, Vo, is given by the fol-

lowing equation:

Vo = (R1/Z + 1) (Vi + Vin)

Since the input voltage, Vin, is small, the gain is given

approximately by the following equation:

AV = Vo/Vi = R1/Z + 1

The ampliﬁer can be used as a voltage ampliﬁer by con-

necting a network to pin 20 as shown in Figure 25. The

bleeder resistor should be chosen to avoid excessive gain

and extreme video sync tip voltages.

Figure 24. Equalization ampliﬁer

Figure 25. Voltage ampliﬁer conﬁguration

External bleeder resistor selection

If the equalization ampliﬁer is conﬁgured for non-unity

gain, bleeder resistors R2 and R3, shown in Figure 26, are

required to ensure that the output DC voltage does not

change.

The sync tip voltage does not change if VX is approxi-

mately equal to V21. VX is given by the following equa-

tion:

VX = VCC × R2/(R2 + R3)

The voltage gain is given by:

AV = 1 + 1000/Z1

where

Z1 = R2

× R3/(R2 + R3)

and resistors R2 and R3 are given by:

R2 = 1000

× V

CC/[(VCC − VX) × (AV − 1)]

R3 = 1000

× V

CC/[VX × (AV − 1)]

Figure 26. External bleeder resistor circuit

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