No. 7099-3/12

LB1929

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

FG amplifier

Input offset voltage

–10

10

mV

Input bias current

IB (FG)

–1

1

µA

Output H level voltage

VREG – 1.2

VREG – 0.8

V

Output L level voltage

0.8

1.2

V

FG input sensitivity

Gain 100-fold

3

mV

Next-stage Schmidt width

Design target value *

100

180

250

mV

Operating frequency range

2

kHz

Open loop GAIN

f (FG) = 2 kHz

45

51

dB

Speed discriminator

Output H level voltage

IDO = –0.1 mA

VREG – 1.0

VREG – 0.7

V

Output L level voltage

IDO = 0.1 mA

0.8

1.1

V

No. of counts

512

PLL output

Output H level voltage

IPO = –0.1 mA

VREG – 1.8

VREG – 1.5

VREG – 1.2

V

Output L level voltage

IPO = 0.1 mA

1.2

1.5

1.8

V

Lock detection

Output L level voltage

0.15

0.5

V

Lock range

6.25

%

Integrator

Input bias current

IB (INT)

–0.4

0.4

µA

Output H level voltage

VREG – 1.2

VREG – 0.8

V

Output L level voltage

0.8

1.2

V

Open loop GAIN

f (INT) = 1 kHz

45

51

dB

Gain-bandwidth product

Design target value *

450

kHz

Reference voltage

Design target value *

–5%

VREG/2

5%

V

Crystal oscillator

Operating frequency range

3

10

MHz

L level pin voltage

VOSCL

IOSC = –0.5 mA

1.65

V

H level pin current

IOSCH

VOSC = VOSCL + 0.3 V

0.4

mA

Start/stop pin

H level input voltage range

3.5

VREG

V

L level input voltage range

0

1.5

V

Input open voltage

VREG – 0.5

VREG

V

Hysteresis width

0.35

0.50

0.65

V

H level input current

V (S/S) = VREG

–10

0

10

µA

L level input current

V (S/S) = 0 V

–280

–210

µA

Forward/reverse pin

H level input voltage range

3.5

VREG

V

L level input voltage range

0

1.5

V

Input open voltage

VREG – 0.5

VREG

V

Hysteresis width

0.35

0.50

0.65

V

H level input current

V (F/R) = VREG

–10

0

10

µA

L level input current

V (F/R) = 0 V

–280

–210

µA

Note*: These items are design target values and are not tested.