LPC122X datasheet(5/60 Pages) NXP

5 / 60 page

LPC122X

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Objective data sheet

Rev. 1.1 — 21 February 2011

5 of 60

NXP Semiconductors

LPC122x

32-bit ARM Cortex-M0 microcontroller

Block diagram

Fig 1.

LPC122x block diagram

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

MICRO DMA

CONTROLLER

system

bus

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT

RESET

SWD

CRC

ENGINE

LPC122x

master

32/48/64/80/

96/128 kB

FLASH

slave

4/8 kB

SRAM

slave

ROM

slave

002aaf269

GPIO ports

WINDOWED WDT

IOCONFIG

RTC

32 kHz OSCILLATOR

SYSTEM CONTROL

CLKOUT

SSP/SPI

UART0 RS-485

I2C

32-bit COUNTER/TIMER 0

SCK

SSEL

MISO

MOSI

4 × MAT

4 × CAP

SDA

SCL

UART1

TXD1

TXD0

RXD1

RXD0

32-bit COUNTER/TIMER 1

4 × MAT

4 × CAP

16-bit COUNTER/TIMER 0

2 × MAT

2 × CAP

16-bit COUNTER/TIMER 1

2 × MAT

2 × CAP

DTR0, DSR0, CTS0,

DCD0, RI0, RTS0

10-bit ADC

MICRO DMA REGISTERS

COMPARATOR0/1

AD[7:0]

ACMP0_I[3:0]

ACMP1_O

ACMP1_I[3:0]

VREF_CMP

ACMP0_O

AHB-LITE BUS

AHB-APB

BRIDGE

HIGH-SPEED

GPIO

RTCXOUT

RTCXIN

IRC, OSCILLATORS

POR

BOD

clocks and controls

Grey-shaded blocks represent peripherals

with connection to the micro DMA

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