65C datasheet(78/112 Pages) RENESAS

78 / 112 page

R01DS0015EJ0100 Rev.1.00

Page 78 of 109

Feb 07, 2011

M16C/65C Group

5. Electrical Characteristics

Figure 5.16

Timing Diagram

BCLK

CSi

ADi

ALE

Hi-Z

DBi

BHE

Read timing

BCLK

CSi

ADi

ALE

BHE

DBi

Write timing

Hi-Z

Memory Expansion Mode and Microprocessor Mode

(in 1 to 3 waits setting and when accessing external area)

= V

= 5V

CC1

CC2

td(BCLK-CS)

25ns(max.)

0ns(min.)

tcyc

th(BCLK-AD)

td(BCLK-AD)

25ns(max.)

td(BCLK-ALE)

15ns(max.)

0ns(min.)

th(BCLK-CS)

-4ns(min.)

th(BCLK-ALE)

0ns(min.)

th(RD-AD)

td(BCLK-RD)

25ns(max.)

0ns(min.)

th(BCLK-RD)

{(n+0.5) × t

-45}ns(max.)

cyc

tsu(DB-RD)

0ns(min.)

th(RD-DB)

td(BCLK-CS)

25ns(max.)

0ns(min.)

th(BCLK-CS)

tcyc

td(BCLK-AD)

25ns(max.)

0ns(min.)

th(BCLK-AD)

td(BCLK-ALE)

15ns(max.)

-4ns(min.)

th(BCLK-ALE)

th(WR-AD)

tac2(RD-DB)

td(BCLK-WR)

25ns(max.)

0ns(min.)

th(BCLK-WR)

td(BCLK-DB)

40ns(max.)

th(WR-DB)

td(DB-WR)

{(n-0.5) × t

-40}ns(min.)

cyc

n: 1 (when 1 wait)

2 (when 2 waits)

3 (when 3 waits)

Measuring conditions

= V

= 5V

CC1

CC2

Input timing voltage: V = 0.8 V, V

= 2.0 V

Output timing voltage: V

= 0.4 V, V

= 2.4 V

f(BCLK)

50ns(min.)

WR, WRL,

WRH

(0.5 × t

- 20)ns(min.)

cyc

(0.5 × t

- 10)ns(min.)

cyc

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