MIC2150 datasheet(13/27 Pages) MICREL

13 / 27 page

Micrel, Inc.

MIC2150

August 2009

M9999-082809-A

(408) 944-0800

DLY

OUT

SET

−

Rcs can now be calculated using:

min

)

MAX

(

DSON

SET

Where:

D = Duty Cycle

FS = Switching Frequency

L = Power inductor value

TDLY = Current limit blanking time ~ 100ns

ICS(min) = 180µA

Example

Consider a 12V to 3.3V @ 5A converter with 0.5µH

power inductor and 90% efficiency at full load.

Efficiency

OUT

≈

µH

kHz

500

)

(

IRIPPLE

−

IPK

µH

100

ISET

−

494

µA

180

RCS

Using the simple method here would result in a current

limit point much lower than expected.

This equation sets the minimum current limit point of the

converter, but maximum will depend on the actual

inductor value and RDSON of the MOSFET under current

limit conditions. This could be in the region of 50%

higher and should be considered to ensure that all the

power components are within their thermal limits unless

thermal protection is implemented separately.

It is recommended to connect a 22pF capacitor from CS

to AGND close to the pins of the IC to prevent adjacent

channel switching noise from affecting the current limit

behavior.

Over Voltage Protection

If the voltage at the FB pin is detected to be 15% higher

than nominal for >2µs, the channel is stopped from

switching immediately and latched off. Switching can be

re-started by taking EN below the channel’s enable

threshold and re-enabling or re-cycling power to the IC.

Power Good Output

The power good output (PG) will go high only when both

Channel outputs are above 90% of their nominal set

output voltage. If CH2 is disabled (EN<2V), then PG will

be low regardless of the state of CH1. If PG functionality

is required for CH1 only, FB2 can be driven externally

above 90% VREF to enable PG to operate on CH1 only.

Enable

Sometimes, at high currents, it is possible to see

relatively large ground current peaks. These, in turn, can

create voltage differentials between AGND points. In

order to prevent these from affecting the converter

operation, it is good practice to drive enable 0.5V higher

than its maximum threshold i.e., >2.8V for both

channels.

VDD Regulator

The internal regulator provides a regulated 5V for

supplying the analogue circuit power (AVDD) and the

MOSFET driver power from the input supply (VIN). While

this is designed to operate in dropout at input voltages

down to 3V, driver current will be limited while the VDD

regulator is in dropout. It is therefore recommended that

for VIN ranges 5V to 7V, MOSFET gate current should be

kept to less than 50mA.

The AVDD supply should be connected to VDD through an

RC filter to provide decoupling of the switching noise

generated by the MOSFET drivers taking large current

steps from the VDD regulator.

Gate Drivers

The MIC2150 is designed to drive both high-side and

low-side N-Channel MOSFETs to enable high switching

speeds and the lowest possible losses. The high-side

MOSFET driver is supplied by bootstrapping the

switching voltage at the Drain of the lower MOSFET to

VDD. This provides the high-side MOSFET with a

constant VGS drive voltage equal to VDD.

Figure 7. High-Side Gate Drive Circuit and Waveform

When HSD goes high, this turns on the high-side

MOSFET and the SW node rises sharply. This is

coupled through the bootstrap capacitor CBST and Diode

DBST becomes reverse biased. The MOSFET Gate is

held at VDD - 0.5V above the Source for as long as CBST

remains charged. The bias current of the high-side driver

is <10mA so 100nF is sufficient to hold the gate voltage

with minimal droop for the power stroke (High-side

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