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LC66P308 Datasheet(PDF) 17 Page - Sanyo Semicon Device |
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LC66P308 Datasheet(HTML) 17 Page - Sanyo Semicon Device |
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17 / 27 page ![]() Continued from preceding page. Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. (Also applies when the Pch open-drain option is selected for P8.) 4. With the output Nch transistor off for pull-up output specification pins. 5. When CMOS output specifications are selected for P8. 6. With the output Nch transistor off for pull-up output specification pins. 7. With the output Pch transistor off for open-drain output specification pins. 8. Reset state Comparator Characteristics at Ta = –30 to +70°C, VSS = 0 V Note: 1. Does not include the quantization error. Figure 1 External Clock Input Waveform No. 5488-17/27 LC66E5316 Parameter Symbol Conditions min typ max Unit Note [Serial output] SO0, SO1: With the timing of Figure 5 and Output delay time tCKO the test load of Figure 5. Stipulated with respect 0.3 µs to the falling edge ( ↓) of SCK0 or SCK1. [Pulse conditions] INT0: Figure 6, conditions under which the INT0 INT0 high and low-level tIOH, tIOL interrupt can be accepted, conditions under 2 Tcyc which the timer 0 event counter or pulse width measurement input can be accepted High and low-level pulse widths tIIH, tIIL INT1, INT2: Figure 6, conditions under which 2 Tcyc for interrupt inputs other than INT0 the corresponding interrupt can be accepted PIN1 high and low-level tPINH, tPINL PIN1: Figure 6, conditions under which the 2 Tcyc pulse widths timer 1 event counter input can be accepted RES high and low-level tRSH, tRSL RES: Figure 6, conditions under which reset 3 Tcyc pulse widths can be applied. Operating current drain IDD OP VDD: 4-MHz ceramic oscillator 6.0 12 mA 8 VDD: 4-MHz external clock 6.0 12 mA VDD: 4-MHz ceramic clock 4 8 mA Halt mode current drain IDDHALT VDD: 32 kHz (main oscillator stopped), 100 500 µA sub-oscillator: crystal Hold mode current drain IDDHOLD VDD: VDD = 1.8 to 5.5 V 0.01 10 µA Parameter Symbol Conditions min typ max Unit Note Absolute precision VCECM AN1 to AN4: VDD = 4.5 to 5.5 V ±1/2 ±1 LSB 1 Threshold voltage VTHCM VDD = 4.5 to 5.5 V VSS VDD V Input voltage VINCM AN1 to AN4: VDD = 4.5 to 5.5 V VSS VDD V Conversion time TCCM VDD = 4.5 to 5.5 V 30 µs textL OPEN (OSC2) OSC1 textR textF VSS VDD 0.2VDD 0.8VDD 1/fext textH External clock |
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