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LC66P516 Datasheet(PDF) 21 Page - Sanyo Semicon Device

Part # LC66P516
Description  Four-Bit Single-Chip Microcontroller with 16 KB of On-Chip EPROM
PDF  26 Pages
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Manufacturer  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC66P516 Datasheet(HTML) 21 Page - Sanyo Semicon Device

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Continued from preceding page.
No. 5486-21/26
LC66E2316
Continued on next page.
Instruction code
Affected
Mnemonic
Operation
Description
status
Note
D7 D6 D5 D4 D3 D2 D1 D0
bits
[Load and store instructions]
Load the contents of M (reg)
into AC. (The reg is either HL
ZF is set
Load AC from M (reg)
AC
← [M (reg)]
or XY.) Then increment the
according to the
LA reg, I
then increment reg
0100
10 t0 11
2
DPL ← (DPL) + 1
contents of either DPL or DPY. ZF
result of
or DPY ← (DPY) + 1 The relationship between t0
incrementing
and reg is the same as that
DPL or DPY.
for the LA reg instruction.
Load the contents of M (reg)
into AC. (The reg is either HL
ZF is set
Load AC from M (reg)
AC
← [M (reg)]
or XY.) Then decrement the
according to the
LA reg, D
then decrement reg
0101
10 t0 11
2
DPL ← (DPL) – 1
contents of either DPL or DPY. ZF
result of
or DPY ← (DPY) – 1
The relationship between t0
decrementing
and reg is the same as that
DPL or DPY.
for the LA reg instruction.
Exchange the contents of
M (reg) and AC.
The reg is either HL or XY
Exchange AC with
depending on t0.
XA reg
M (reg)
0100
11 t0 0
1
1
(AC)
↔ [M (reg)]
Exchange the contents of
M (reg) and AC. (The reg is
ZF is set
Exchange AC with
(AC)
↔ [M (reg)]
either HL or XY.) Then
according to the
XA reg, I M (reg) then
0100
11 t0 11
2
DPL ← (DPL) + 1
increment the contents of
ZF
result of
increment reg
or DPY ← (DPY) + 1
either DPL or DPY. The
incrementing
relationship between t0 and
DPL or DPY.
reg is the same as that for
the XA reg instruction.
Exchange the contents of
M (reg) and AC. (The reg is
ZF is set
Exchange AC with
(AC)
↔ [M (reg)]
either HL or XY.) Then
according to the
XA reg, D M (reg) then
0101
11 t0 11
2
DPL ← (DPL) – 1
decrement the contents of
ZF
result of
decrement reg
or DPY ← (DPY) – 1
either DPL or DPY. The
decrementing
relationship between t0 and
DPL or DPY.
reg is the same as that for
the XA reg instruction.
XADR i8
Exchange AC with
1100
1000
2
2
(AC)
↔ [M (i8)]
Exchange the contents of AC
M direct
I7 I6 I5 I4 I3 I2 I1 I0
and M (i8).
LEAI i8
Load E & AC with
1100
0110
22
E
← I
7 I6 I5 I4
Load the immediate data i8
immediate data
I7 I6 I5 I4 I3 I2 I1 I0
AC
← I
3 I2 I1 I0
into E, AC.
Load into E, AC the ROM data
RTBL
Read table data from
0101
1010
1
2
E, AC
←
at the location determined by
program ROM
[ROM (PCh, E, AC)]
replacing the lower 8 bits of
the PC with E, AC.
Output from ports 4 and 5 the
Read table data from
Port 4, 5
←
ROM data at the location
RTBLP
program ROM then
0101
1000
1
2
[ROM (PCh, E, AC)]
determined by replacing the
output to P4, 5
lower 8 bits of the PC with
E, AC.
[Data pointer manipulation instructions]
Load DPH with zero
LDZ i4
and DPL with
0110
I3 I2 I1 I0
11
DPH ← 0
Load zero into DPH and the
immediate data
DPL
← I
3 I2 I1 I0
immediate data i4 into DPL.
respectively
LHI i4
Load DPH with
1100
1111
22
DPH ← I3 I2 I1 I0
Load the immediate data i4
immediate data
0000
I3 I2 I1 I0
into DPH.
LLI i4
Load DPL with
1100
1111
22
DPL ← I3 I2 I1 I0
Load the immediate data i4
immediate data
0001
I3 I2 I1 I0
into DPL.
LHLI i8
Load DPH, DPL with
1100
0000
22
DPH ← I7 I6 I5 I4
Load the immediate data into
immediate data
I7 I6 I5 I4 I3 I2 I1 I0
DPL ← I3 I2 I1 I0
DLH, DPL.
LXYI i8
Load DPX, DPY with
1100
0000
22
DPX ← I7 I6 I5 I4
Load the immediate data into
immediate data
I7 I6 I5 I4 I3 I2 I1 I0
DPY ← I3 I2 I1 I0
DLX, DPY.
reg
T0
HL
0
XY
1



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