Micrel, Inc.

SY56017R

July 2008

3

M9999-070308-A

hbwhelp@micrel.com or (408) 955-1690

Pin Description

Pin Number

Pin Name

Pin Function

16,1

4,5

IN0, /IN0

IN1, /IN1

or 27 inches 6 mil FR4 stripline transmission line are then terminated with the differential

input . Each input pin internally terminates with 50

Ω to the VT pin.

2

3

VT0

VT1

Input Termination Center-Tap: Each side of the differential input pair terminates to a VT

pin. This pin provides a center-tap to a termination network for maximum interface

flexibility. An internal high impedance resistor divider biases VT to allow input AC-

coupling. For AC-coupling, bypass VT with 0.1µF low ESR capacitor to VCC. See

“Interface Applications” subsection and Figure 2a.

6

EQ

Three level input for equalization control. High, float, low. EQ pin applies the same EQ

setting to both inputs.

15

SEL

This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note

that this input is internally connected to a 25k

Ω pull-up resistor and will default to a logic

HIGH state if left open.

7

VCC

pins as possible. Supplies input and core circuitry.

8,13

VCCO

as possible. Supplies the output buffers.

14

GND,

Exposed pad

Ground: Exposed pad must be connected to a ground plane that is the same potential as

the ground pins.

11,10

Q, /Q

CML Differential Output Pair: Differential buffered copy of the input signal. The output

swing is typically 390mV. See “Interface Applications” subsection for termination

information.