No. 6166-5/33

LC72710W, 72710LW

[LC72710LW]

Notes:

Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.

When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait

time) settings for the CPU bus.

If the RDY signal is not used, (that is, if no wait states are inserted) the value of the “RD low-level width“ will be 280 ns (minimum).

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Address to RD setup

A0/CL, A1/CE, A2/DI, A3, RD

20

ns

RD to address hold

–20

ns

RD low-level width

RD

280

ns

RD low-level width (when RDY is used)

RD

100

280

ns

RD cycle wait

A0/CL, A1/CE, A2/DI, A3, RD

150

ns

RDY width (Register read)

RDY

60

230

ns

RD data hold

RD, DATn

0

ns

Address to WR setup

A0/CL, A1/CE, A2/DI, A3, WR

20

ns

WR to address hold

A0/CL, A1/CE, A2/DI, A3, WR

20

ns

WR cycle wait

A0/CL, A1/CE, A2/DI, A3, WR

150

ns

WR low-level width

WR

200

ns

WR data hold

WR, DATn

0

ns

RDY output delay

RD, RDY

0

50

ns

Corrected output RD width

RD (BUSWD = L 8 bits)

300

ns

RD (BUSWD = H 16 bits)

540

ns

Corrected output RD width

RD (BUSWD = L 8 bits)

100

300

ns

(when RDY is used)

RD (BUSWD = H 16 bits)

300

540

ns

RDY width (corrected output read)

RDY (BUSWD = L 8 bits)

60

230

ns

RDY ((BUSWD = H 16 bits)

300

490

ns

DACK to DREQ delay

DREQ, DACK

260

ns

DMA cycle wait

RD, DREQ

420

ns

RD low-level width (DMA)

RD

300

ns