SX8725 datasheet(21/53 Pages) SEMTECH

21 / 53 page

ADVANCED COMMUNICATIONS & SENSING

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SX8725

ZoomingADC™ for Pressure and Temperature Sensing

PGA & ADC Enabling

Depending on the application objectives, the user may enable or bypass each PGA stage. This is done

according to the word ENABLE and the coding given in Table 4. To reduce power dissipation, the ADC can also

be inactivated while idle.

PGA1

The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 5). The voltage VD1 at

the output of PGA1 is:

⋅

(V)

Equation 5

where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN.

PGA2

The second PGA has a finer gain and offset tuning capability, as shown in Table 6 and Table 7. The voltage VD2

at the output of PGA2 is given by:

ADC

REF

GDoff

⋅

−

⋅

(V)

Equation 6

where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the

words PGA2_GAIN[1:0] and PGA2_OFFSET[3:0].

PGA3

The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of

Table 8 and Table 9. The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the

voltage entering the ADC is given by:

ADC

REF

ADC

GDoff

⋅

−

⋅

(V)

Equation 7

where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are

PGA3_GAIN[6:0] and PGA3_OFFSET[6:0]. To remain within the signal compliance of the PGA stages, the

condition:

1 ,

(V)

Equation 8

must be verified.

Finally, combining equations 5 to 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related to

VIN by:

ADC

REF

TOT

ADC

GDoff

⋅

−

⋅

(V)

Equation 9

where the total PGA gain is defined as:

TOT

⋅

(V/V)

Equation 10

and the total PGA offset is:

GDoff

TOT

⋅

(V/V)

Equation 11

SX8725 Datasheet(PDF) 21 Page - Semtech Corporation

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