Analog Integrated Circuit Device Data

6

Freescale Semiconductor

33882

PIN CONNECTIONS

16

SCLK

Serial Clock

The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It transitions one

time per bit transferred when in operation. It is idle between command transfers. It is

50% duty cycle, and has CMOS levels.

17

CS

Chip Select

This pin is connected to a chip select output of the control IC.This input has an

internal active 25

μA pull-up and requires CMOS logic levels.

18

SO

Serial Output

This pin is connected to the SPI Serial Data Input pin of the control IC or to the SI pin

of the next device in a daisy chain. This output will remain tri-stated unless the device

will have CMOS logic levels and the output data will transition on the falling edges of

SCLK. The serial output data provides fault information for each output and is

returned MSB first when the device is addressed.

23

Logic Supply Voltage

This pin is connected to the 5.0 V power supply of the system. A decoupling

Table 2. QFN Pin Function Description

Pin

Pin Name

Formal Name

Definition