33892 datasheet(19/28 Pages) FREESCALE

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33892

Device Register Addressing

The following section describes the possible register

addresses and their impact on device operation.

Address xx000—Status Register (STATR)

The STATR register is used to read the device status and

the various configuration register contents without disrupting

the device operation or the register contents. The register bits

D[4:0] determine the content of the first sixteen bits of SO data.

In addition to the device status, this feature provides the ability

to read the content of the OCR0, OCR1, SOCHLR, CDTOLR,

DICR, UOVR, WDR, and NAR registers. (Refer to the section

entitled Serial Output Communication (Device Status Return

Data) beginning on page 21.)

Address x0001—Output Control Register (OCR0)

The OCR0 register allows the MCU to control the ON/OFF

state of four outputs through the SPI. Incoming message bit

D[3:0] reflects the desired states of the four high-side outputs

(IN_SPI), respectively. A logic [1] enables the corresponding

output switch and a logic [0] turns it OFF.

Address x1001—Output Control Register (OCR1)

Incoming message bit D[3:0] reflects the desired channel

that will be mirrored on the Current Sense (CSNS) terminal. A

logic [1] on message bit D[3:0] enables the CSNS terminal for

the outputs HS3–HS0, respectively. In the event that the

current sense is enabled for multiple outputs, the current will be

summed. In the event that all bits D[3:0] are logic [0], the output

CSNS will then tri-stated. This is useful when several CSNS

terminals of several devices share the same A/D converter.

Address A1A0010—Select Overcurrent High and Low

The SOCHLR_s register allows the MCU to configure the

output overcurrent low and high detection levels, respectively.

Each output “s” is independently selected for configuration

based on the state of the D12–D11 bits (Table 3).

Each output can be configured to different levels. In addition

to protecting the device, this slow blow fuse emulation feature

can be used to optimize the load requirements matching

system characteristics. Bits D2–D0 set the overcurrent low

detection level to one of eight possible levels, as shown in

Table 4, page 20. Bit D3 sets the overcurrent high detection

level to one of two levels, as outlined in Table 5, page 20.

Table 2. Serial Input Address and Configuration Bit Map

SI Register

SI Data

D15

D14 D13 D12 D11 D10 D9

STATR

WDIN

SOA4

SOA3

SOA2

SOA1

SOA0

OCR0

WDIN

IN_SPI3

IN_SPI2

IN_SPI1

IN_SPI0

OCR1

WDIN

CSNS EN3

CSNS EN2

CSNS EN1 CSNS EN0

SOCHLR_s

WDIN

SOCH_s

SOCL2_s

SOCL1_s

SOCL0_s

CDTOLR_s

WDIN

OL_DIS_s

OCL_DIS_s

OCLT1_s

OCLT0_s

DICR_s

WDIN

FAST_SR_s CSNS_high_s DIR_DIS_s

A/O_s

UOVR

WDIN

UV_DIS

OV_DIS

WDR

WDIN

WD1

WD0

NAR

WDIN

No Action (Allow Toggling of D15–WDIN)

TEST

WDIN

Motorola Internal Use (Test)

x=Don’t care.

s=Output selection with the bits A1A0 as defined in Table 3.

Table 3. Channel Selection

A1 (D12)

A0 (D11)

HS_s

HS0

HS1

HS2

HS3

Freescale Semiconductor, Inc.

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