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LC75816W Datasheet(PDF) 13 Page - Sanyo Semicon Device |
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LC75816W Datasheet(HTML) 13 Page - Sanyo Semicon Device |
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13 / 43 page ![]() No. 7142-13/43 LC75816E, 75816W SC: Controls the common and segment output pins Note: *13. When SC is 1, the S1 to S65 and COM1 to COM10 output pins are set to the VLCD4 level, regardless of the M, A, and DG1 to DG13 data. SC Common and segment output pin states 0 Output of LCD drive waveforms 1 Fixed at the VLCD4 level (all segments off) SP: Controls the normal mode and sleep mode SP Mode 0 Normal mode Sleep mode 1 (The common and segment pins go to the VLCD4 level and the oscillator on the OSCI, OSCO pins is stopped (although it operates during key scan operations), to reduce current drain. Although the "display on/off control", "set display contrast", and "set key scan output port/general- purpose output port state" instructions can be executed in this mode, applications must return the IC to normal mode to execute any of the other instruction settings.) • Display shift ... <Shifts the display> Code D56 D57 D58 D59 D60 D61 D62 D63 M A R/L X 0 0 1 1 X: don’t care M, A: Specifies the data to be shifted M A Shift operating state 0 0 Neither MDATA nor ADATA is shifted 0 1 Only ADATA is shifted 1 0 Only MDATA is shifted 1 1 Both MDATA and ADATA are shifted R/L: Specifies the shift direction R/L Shift direction 0 Shift left 1 Shift right X: don’t care • Set AC address... <Specifies the DCRAM and ADRAM address for AC> Code D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DA0 DA1 DA2 DA3 DA4 DA5 X X RA0 RA1 RA2 RA3 0 1 0 0 DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 DA4 DA5 LSB ↑ Least significant bit MSB ↑ Most significant bit RA0 to RA3: ADRAM address RA0 RA1 RA2 RA3 LSB ↑ Least significant bit MSB ↑ Most significant bit This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC. |
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