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CY3672-USB Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY3672-USB
Description  One-PLL General-Purpose Flash-Programmable Clock Generator
PDF  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY3672-USB Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY22050,
CY220501
Document #: 38-07006 Rev. *I
Page 7 of 11
t4HI
Falling edge slew rate
(VDDL = 3.3 V)
Output clock fall time, 80% – 20% of VDD/VDDL.
Defined in Figure 5
0.8
1.4
V/ns
t5[7]
Skew
Output-output skew between related outputs
250
ps
t6[8]
Clock jitter
Peak-to-peak period jitter (see Figure 6)250
ps
t10
PLL lock time
0.30
3
ms
AC Electrical Characteristics
Parameter[4]
Name
Description
Min
Typ.
Max
Unit
Figure 3. Test Circuit
Figure 4. Duty Cycle Definition: DC = t2/t1
Figure 5. Rise and Fall Time Definitions
Figure 6. Peak-to-Peak Jitter
0.1
μF
VDD
0.1
μF
AVDD
CLK out
CLOAD
GND
OUTPUTS
VDDL
0.1
μF
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
CLK
t6
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