CY22050,

CY220501

Document #: 38-07006 Rev. *I

Page 2 of 11

Pin Configuration

Figure 1. 16-Pin TSSOP

Table 1. Pin Definitions

Name

Pin Number

Description

XIN

1

Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).

Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based on

manufacturer, process, performance, or quality.

VDD

2

3.3 V voltage supply

AVDD

3

3.3 V analog voltage supply

PWRDWN[1]

4

Power Down. When pin 4 is driven LOW, the CY22050 goes into shut down mode.

AVSS

5

Analog ground

VSSL

6

LCLK ground

LCLK1

7

LCLK2

8

LCLK3

9

OE[1]

10

Output Enable. When pin 10 is driven LOW, all outputs are three-stated.

VDDL

11

LCLK voltage supply (2.5 V or 3.3 V)

LCLK4

12

VSS

13

Ground

CLK5

14

Configurable clock output 5 (3.3 V)

CLK6

15

Configurable clock output 6 (3.3 V)

XOUT[2]

16

Reference output

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VSS

VSSL

OE

LCLK1

XIN

XOUT

VDD

PWRDWN

AVSS

LCLK3

LCLK2

CLK6

CLK5

AVDD

VDDL

LCLK4

Notes

1. The CY22050 has no internal pull up or pull down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground.

2. Float XOUT if XIN is driven by an external clock source.

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