AP9050 datasheet(4/9 Pages) DIODES

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AP9050

PROTECTION INTERFACE for PMICs with

INTEGRATED OVP CONTROL

AP9050

Document number: DS35283 Rev. 1 - 2

4 of 9

www.diodes.com

March 2011

Electrical Characteristics (VIN (OVP_SENSE) = 5.0V, TJ = +25°C, unless otherwise noted)

Symbol

Parameter

Test Conditions

Min

Typ.

Max

Unit

Power FET

IDSS

Zero Gate Voltage Drain Current

VDS = 24V, VGS = 0V

TJ = 85°C

1.0

µA

IGSS

Gate-to-Source Leakage Current

VDS = 0V, VGS = ±8V

VGS(th)

Gate Threshold Voltage

VGS = VDS, ID = 250µA

0.62

0.9

1.2

RDS(on)

Drain-to-Source On-Resistance

(Note 7)

VGS = 4.5V, ID = 2.0A

VGS = 2.5V, ID = 2.0A

Ω

gFS

Forward Transconductance

VDS = 5V, ID = 2.0A

CISS

Input Capacitance

VDS = 15V, VGS = 0V,

f = 1MHz

500

COSS

Output Capacitance

VDS = 15V, VGS = 0V,

f = 1MHz

CRSS

Reverse Transfer Capacitance

VDS = 15V, VGS = 0V,

f = 1MHz

LDO (unless otherwise noted, TJ = 25ºC, VIN = 5.0V)

VOUT

Regulated Output Voltage

VIN = 5.5V, IOUT = 1mA

4.6

5.0

5.3

Vhead

Headroom

VIN − VOUT, IOUT = 1.2mA,

VIN = 4.6V

150

VIN − VOUT, IOUT = 10mA,

VIN = 4.8V, TJ = −40 to +125°C

1000

Response to Input Transient

tpulse

Time signal is above 5.5V

VIN 0 to 30V, < 1µs rise time,

5.0k

Ω resistive load (Note 8)

5.0

µs

Vpk

Peak Voltage

VIN 0 to 30V, < 1µs rise time,

5.0k

Ω resistive load (Note 8)

9.0

Total Device

Ibias

Input Bias Current

VIN = 5.5V

110

850

µA

VIN_min

Minimum Operating Voltage

3.0

Notes:

7. Pulse test width 300µs, duty cycle 2%

8. Guaranteed by design

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