Micrel, Inc.

MIC5191

December 2006

8

M9999-122206

Application Information

Designing with the MIC5191

Anatomy of a transient response

A voltage regulator can maintain a set output voltage

while its exterior world is pushing and pulling in its

demand for power. The measure of a regulator is

generally how accurately and effectively it can maintain

that voltage, regardless of how the load demands power.

One measure of regulator response is the load step.

This is an intuitive look at how the regulator responds to

a change in load current. Figure 2 is a look at the

transient response to a load step.

Time

it

C

V

1

BW

1

Output voltage vs. Time

during recovery is

directly proportional to

gain vs. frequency

Figure 2. Typical Transient Response

At the start of a circuit's power demand, the output

voltage is regulated to its set point, while the load current

runs at a constant rate. For many different reasons, a

load may ask for more current without warning. When

this happens, the regulator needs some time to

determine the output voltage drop. This is determined by

the speed of the control loop. So, until enough time has

elapsed, the control loop is oblivious to the voltage

change. The output capacitor must bear the burden of

maintaining the output voltage.

dt

di

L

∆V

=

Since this is a sudden change in voltage, the capacitor

will try to maintain voltage by discharging current to the

output. The first voltage drop is due to the output

capacitor's ESL (equivalent series inductance). The ESL

will resist a sudden change in current from the capacitor

and drop the voltage quickly. The amount of voltage

drop during this time will be proportional to the output

capacitor's ESL and the speed at which the load steps.

Slower load current transients will reduce this effect.

↑

↓=

dt

di

L

∆V

Placing multiple small capacitors with low ESL in parallel

can help reduce the total ESL and reduce voltage droop

during high speed transients. For high speed transients,

the greatest voltage deviation will generally be caused

by output capacitor ESL and parasitic inductance.

dt

di

L

∆V

↓

↓=

After the current has overcome the effects of the ESL,

the output voltage will begin to drop proportionally to

time and inversely proportional to output capacitance.

∫

=

idt

C

1

∆V

The relationship to output voltage variation will depend

on two aspects, loop bandwidth and output capacitance.

The output capacitance will determine how far the

voltage will fall over a given time. With more capacity-

ance, the drop in voltage will fall at a decreased rate.

This is the reason that for the same bandwidth, more

capacitance provides a better transient response.

∫

↑

↓=

idt

C

1

∆V

Also, the time it takes for the regulator to respond is

directly proportional to its gain bandwidth. Higher

bandwidth control loops respond quicker causing a

reduced droop on the supply for the same amount of

capacitance.

↓=

idt

C

1

∆V

Final recovery back to the regulated voltage is the final

phase of transient response and the most important

factors are gain and time. Higher gain at higher

frequency will get the output voltage closer to its

regulation point quicker. The final settling point will be

determined by the load regulation, which in proportional

to DC (0Hz) gain and the associated loss terms.

There are other factors that contribute to large signal

transient response, such as source impedance, phase

margin and PSRR. For example, if the input voltage

drops due to source impedance during a load transient,

this will contribute to the output voltage deviation by

filtering through to the output reduced by the loops

PSRR at the frequency of the voltage transient. It is

straightforward: good input capacitance reduces the

source impedance at high frequencies. Having between

35° and 45° of phase margin will help speed up the

recovery time. This is caused by the initial overshoot in

response to the loop sensing a low voltage.