ADC1213S datasheet(21/39 Pages) NXP

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ADC1213S_SER

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Product data sheet

Rev. 1 — 14 March 2011

21 of 39

NXP Semiconductors

ADC1213S series

Single 12-bit ADC; serial JESD204A interface

11.5 JESD204A serializer

For more information about the JESD204A standard refer to the JEDEC web site.

11.5.1 Digital JESD204A formatter

The block placed after the ADC core is used to implement all functions of the JESD204A

standard. This ensures signal integrity and guarantees the clock and the data recovery at

the receiver side.

The block is highly parameterized and can be configured in various ways depending on

the sampling frequency and the number of lanes used.

Fig 20. CML output connection to the receiver (AC-coupling)

CMLP

CMLN

12 mA to 26 mA

100 Ω

50 Ω

10 nF

005aaa187

VDDD

RECEIVER

Fig 21. General overview of the JESD204A serializer

FRAME

OCTETS

F octets

SCRAMBLER

TX transport layer

CF: position of controls bits

HD: frame boundary break

Padding with Tails bits (TT)

× (N' × S) bits

× (F) octets

L octets

N' = N + CS

S samples per frame cycle

N bits from Cr0 +

CS bits for control

M CONVERTERS

L LANES

TX CONTROLLER

LANE 0

8-bit/

10-bit

SER

ALIGNMENT

CHARACTER

GENERATOR

SYNC~

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