DS31407

3

Detailed Features

Input Clock Features



Three input clocks, differential or CMOS/TTL signal format

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Input clocks can be any frequency from 2kHz up to 750MHz

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Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3



Per-input fractional scaling (i.e. multiplying by N

D where N is a 16-bit integer and D is a 32-bit integer and

N < D) to undo 64B/66B and FEC scaling (e.g., 64/66, 238/255, 237/255, 236/255)



Special mode allows locking to 1Hz input clocks

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All inputs constantly monitored by programmable activity monitors and frequency monitors

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Fast activity monitor can disqualify the selected reference after a few missing clock cycles

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Frequency measurement and frequency monitor thresholds with 0.2ppm resolution

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Three optional 2/4/8kHz frame-sync inputs

DPLL Features



Very high-resolution DPLL architecture

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Sophisticated state machine automatically transitions between free-run, locked, and holdover states

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Revertive or nonrevertive reference selection algorithm

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Programmable bandwidth from 0.5mHz to 400Hz

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Separately configurable acquisition bandwidth and locked bandwidth

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Programmable damping factor: 1.2, 2.5, 5, 10, or 20



Multiple phase detectors: phase/frequency and multicycle

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Phase/frequency locking (

360 capture) or nearest edge phase locking (180 capture)



Multicycle phase detection and locking (up to

8191UI) improves jitter tolerance and lock time



Phase build-out in response to reference switching for true hitless switching



Less than 1 ns output clock phase transient during phase build-out



Output phase adjustment up to

200ns in 6ps steps with respect to selected input reference

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High-resolution frequency and phase measurement

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Holdover frequency averaging over 1-second, 5.8-minute, and 93.2-minute intervals



Fast detection of input clock failure and transition to holdover mode

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Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks

Digital Frequency Synthesizer Features

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Two independently programmable DFS engines

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Each DFS can synthesize any 2kHz multiple up to 77.76MHz



Per-DFS phase adjust (1/256UI steps)



Approximately 40ps RMS output jitter

Output APLL Features



Simultaneously produce four different output frequencies from the same reference clock



Standard telecom output frequencies include 622.08MHz, 155.52MHz, and 19.44MHz for SONET/SDH

and 156.25MHz, 125MHz, and 25MHz for Synchronous Ethernet



Very high-resolution fractional scaling (i.e., noninteger multiplication)

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Less than 1ps RMS output jitter

ABRIDGED DATA SHEET